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Course contents

  • How to Use This Course
  • The NanoSoC Tour
  • Reading Path
  • SoC Glossary10
  • SoC Metrics Reference
  • SoC Cheatsheet
  • What SoC Integration Is12
  • Architecture and Budgets21
  • Memory Maps and Address Decode26
  • Interconnect and Bus Fabrics26
  • Clock and Reset Architecture24
    • Clock Sources and PLLs
    • Dividers, Muxes and Glitch-Free Switching
    • Clock Gating Architecture
    • Clock Domain Planning
    • Top-Level Crossings
    • Always-On Domain, Wake Policy and a Timer Extension
    • Reset Sources and Reset Tree
      • Reset Sources
      • The Reset Tree per Domain
      • Reset Controller Registers and Software View
    • Reset Sequencing and Release
  • Power Architecture21
  • Interrupts, DMA and Peripherals15
  • Memories, Boot and Security21
  • IP Integration and Handoff21
  • Top-Level Verification and Bring-up21
  • Package, Pads and I/O18
  • Chip Signoff and Tapeout18
  • SoC Interview Prep16
  • Capstone: Integrate NanoSoC14
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←Clock and Reset Architecture
  1. Topics
  2. SoC Design
  3. Clock and Reset Architecture
  4. Reset Sources and Reset Tree

Part 5 of 14Part 5 of 14/Clock and Reset ArchitectureAll levels

Reset Sources and Reset Tree

POR, pad, software and wake resets, per-domain nets, and the NanoSoC reset tree.

  • 3topics
  • 3lessons

Four sources can reset NanoSoC, three nets carry reset to the flops, and one register remembers why. This topic names the sources, draws the tree per domain, and teaches the controller's register view that software reads first after every reset. The release order and its timing are the next topic; here the question is what resets what. For the RTL view see Reset Tree Planning and Reset Sequencing and POR Controller.

Lesson

After it you can...

Reset Sources

Name all four sources, their conditions and what each one resets.

The Reset Tree per Domain

Trace each net from its source to every flop it reaches.

Reset Controller Registers and Software View

Read RST_CAUSE first and drive a software reset correctly.

Suggested order: top to bottom. Sources first, because the tree multiplexes them; then the tree, because the register view reports on it; then the software view, which is read in bring-up order. The release sequence in the next topic assumes every net drawn here.

Check yourself Why do four sources fan into three nets rather than resetting the whole chip together?

Different events need different scopes: a software reset must not wipe the always-on controller that issued it, and a wake reset must not clear the retained memory the resume needs. Per-domain nets let each source reset exactly what its recovery requires.

Expect to draw the four sources on the left, the three nets on the right, and the cause register underneath. Then answer which source leaves SRAM0 intact: all except supply loss.

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See also

  • Clock Sources and PLLs
  • Dividers, Muxes and Glitch-Free Switching
  • Clock Gating Architecture