NanoSoC stops three clocks when their logic has nothing to do: the CPU clock on a wait-for-interrupt, the DMA and stream-bridge clocks on register bits. Stopping a clock saves power but can hang a bus, freeze a wake-up or slice a pulse in half, so every gate has an owner, a timing rule and a wake path. This topic teaches the cell that makes gating safe, the hierarchy that decides who gates what, and the failure where the DMA clock stops in the middle of a bus access. For the RTL cell view see Clock Gating and The ICG Cell; for the CDC view see Clock Gating and Muxing.
Lesson | After it you can... |
|---|---|
Explain the latch-based cell, its setup and hold, and prove a model glitch-free. | |
Assign every NanoSoC gate an owner and a wake path. | |
Tell the DMA gating failure as symptom, capture and fix, and write its check. |
Suggested order: top to bottom. The cell first, because the hierarchy assumes glitch-free gates; then ownership, because the failure is an ownership mistake; then the failure itself. Readers who gate clocks in RTL already can start at the second lesson.
Because the enable for one block depends on the state of others: the DMA must be idle, its bus quiet and its interrupt cleared before its clock stops. Only the integrator sees all three, so only the integrator can own the rule.