Gated and muxed clocks sit exactly on the fault line of this course: they save power and add flexibility, but every gate and mux is a place where a runt pulse or a stopped clock can corrupt a crossing. This topic treats them as domain boundaries with rules, not as wiring details.
For the gating cell itself, the clock gating lessons in the RTL course cover the latch-based gate, enable quality, and timing checks. Nothing here repeats that; it builds on it.
Lesson | After it you can... |
|---|---|
Describe the safe mux structure and show a simulation with no runt pulses. | |
Say when a gated clock shares its parent domain and when the enable path is a crossing. | |
Keep handshakes alive when a clock may stop. | |
Order resets and state correctly across a clock-source change. |
Because gated and muxed clocks decide what the domains even are. Until each gated clock is classified as same-domain or separate, the crossing inventory cannot be written.