Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • How to Use This Course
  • Reading Path
  • CDC/RDC Glossary
  • CDC/RDC Metrics Reference
  • CDC/RDC Interview Prep
  • CDC/RDC Signoff Cheatsheet
  • Clock Domains and Failure Modes8
  • Metastability and Synchronizers16
  • CDC Protocols and Handshakes16
  • Reconvergence and Gray Coding16
  • Reset Domain Crossing16
  • Architecture and Design Rules16
    • CDC-Aware Partitioning
    • Clock Gating and Muxing
      • Glitch-Free Clock Mux
      • Gating as a Domain Boundary
      • Crossing with Gated Clocks
      • Clock Switching and Reset
    • Interface and IP Rules
    • Quasi-Static Signals and Configuration
  • CDC Signoff Methodology24
  • RDC Signoff16
  • Debug and Case Studies11
  • CDC and RDC Interview Prep30
  • Capstone: Sign Off a Multi-clock Peripheral4
Loading lesson

‹Clock Gating and Muxing
  1. Topics
  2. CDC & RDC
  3. Architecture and Design Rules
  4. Clock Gating and Muxing
  5. Gating as a Domain Boundary

Part 6 · Architecture and Design Rules · Intermediate

Gating as a Domain Boundary

When a gated clock is one domain with its parent and when enable timing creates crossings; the enable path.

On this page

    A gated clock is the same clock with some edges removed, so logic on the gated clock and logic on its parent are usually one timing domain: the clock-tree tool balances them together and static timing covers the paths between them. That pleasant fact holds only while the enable behaves, which is why the enable path gets its own rules.

    One domain, with conditions

    Condition

    Why it matters

    The gate is a library cell with characterised timing

    Static timing models the enable setup and hold checks and the gated-clock delay (see clock gating).

    Enable meets its gating checks at every corner

    A late enable shortens or drops a pulse; the domain assumption rests on this check passing.

    Trees are balanced through the gate

    Skew between gated and ungated flops is bounded by construction, not by luck.

    The enable is synchronous to the parent clock

    An enable from another domain is a crossing and needs synchronising first.

    When all four hold, a path from an ungated flop to a gated flop is an ordinary same-clock path. No synchroniser, no handshake, no inventory row beyond noting the gating.

    The enable path

    The enable is the fragile part. It launches from a flop on the parent clock and must arrive at the gate before the latch closes, a full-cycle path that is easy to meet when the enable is registered but easy to break when it is decoded from deep logic. A late enable is reported as a clock-gating setup violation, and a design that waives those violations has silently turned one domain into an unanalysed one.

    A gated clock sharing its parent timing domain.
    The enable launches from the parent clock; gated and ungated flops exchange data as one domain while the gating checks pass.

    When to treat the gated clock as a separate domain

    • The enable comes from another clock domain. Synchronise it first; the synchronised enable is still on the parent clock, but the unsynchronised wire is a crossing.

    • The gating is implemented outside the standard flow, for example with hand-built logic instead of a library cell. Without characterised checks, timing between the two sides is not proven.

    • The gated clock can be stopped for long periods while the parent runs. Timing is still one domain, but functionally the crossing lessons of crossing with gated clocks apply.

    Common pitfall

    Deriving the enable combinationally from the outputs of the gated flops themselves. When the clock stops, those outputs freeze; if the frozen value keeps the enable low, the block can never wake up. The enable must depend on something that moves while the gated clock is still.

    Check yourself A gated block and its parent exchange data every cycle with no synchronisers, and timing is clean. A new feature drives the gate enable from a different clock domain. What must change?

    The enable path is now a crossing: synchronise the new enable into the parent domain before it reaches the gate, and add the crossing to the inventory. The data paths stay same-domain; only the enable changed character.

    Related topics

    • Glitch-Free Clock Mux

    • Crossing with Gated Clocks

    • RTL: Clock Gating

    Previous

    84 / 179

    Next: Crossing with Gated Clocks

    Up next

    Up nextCrossing with Gated Clocks

    Sign in to save progress

    Practice this lessonReport an error

    See also

    • Clock Switching and Reset