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Course contents

  • RTL Foundations36
  • Combinational Design25
  • Sequential Design27
    • Flip-Flops and Registers
    • Counters and Timers
      • Counting as Controlled State Evolution
      • Up/Down Counter with Reload
      • A Prescaler Feeding a Timer Tick
      • Watchdog Timer Example
      • A Gray-Code Counter
      • Mini Project: a Programmable Timer
    • Shift Registers and LFSRs
    • Pipelining
    • Stalls, Bubbles and Hazards
    • Retiming
  • FSM & Control27
  • Timing & Clocking39
  • Reset & CDC34
  • Memory & Buses57
  • Advanced RTL28
  • Senior & Interview76
  • Glossary and Notation
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‹Counters and Timers
  1. Topics
  2. RTL Design
  3. Sequential Design
  4. Counters and Timers
  5. Watchdog Timer Example

Part 3 · Sequential · Intermediate

Watchdog Timer Example

A counter that fires a sticky timeout flag unless it is kicked regularly.

On this page

    Why this matters

    A watchdog that shares the failing clock cannot see that clock fail, and one that fires a cycle off breaks the recovery budget. The design questions matter as much as the counter.

    After this lesson you can: build a watchdog with kick, disable and a sticky timeout, and list the design questions to settle before coding it.

    What a watchdog does

    A watchdog guards against a stuck system. A periodic kick clears its counter; silence for the full limit raises a timeout used to reset the system.

    State diagram with Counting and Fired states and the kick, timeout and reset transitions.
    Kicks keep the watchdog in the Counting state; silence for TIMEOUT cycles moves it to Fired.

    Timeout, kick, and disable behavior

    The counter clears on kick or while disabled, and sets a sticky timeout after TIMEOUT kick-free cycles. The exact interval is tested to the cycle in the testbench below.

    Each slot is one clock cycle, sampled just after its rising edge; en is high throughout. A kick drawn in slot k acts at the edge that opens slot k+1.

    • Slots 0 to 2: the count climbs 0, 1, 2; the kick in slot 2 clears it to 0 in slot 3.

    • Slots 4 to 6: no kick, so the count runs 1, 2, 3. In slot 6 it equals TIMEOUT − 1.

    • Slot 7: the edge that found 3 sets timeout, four edges after the kick edge. The count stops at 3.

    • Slots 8 to 10: a late kick clears the count, but timeout stays high. Only reset clears it.

    TIMEOUT may be 1 (fires after one enabled cycle without a kick): the counter width is guarded as localparam int CW = (TIMEOUT > 1) ? $clog2(TIMEOUT) : 1; because $clog2(1) is 0.

    Design questions to settle

    Question

    Typical choice

    Sticky timeout or pulse?

    Sticky: the system must see the event even if it is busy; clear it by reset.

    What does a kick do?

    Clears the counter. Some designs require a specific kick pattern so a runaway program cannot keep feeding it by accident.

    Can software disable it?

    Often only before the first kick or via a protected register, so a bug cannot silently turn it off.

    Window watchdog?

    A kick that arrives too early is also an error, which detects a loop that kicks too fast.

    Which clock runs it?

    Ideally an independent, always-on clock so a clock failure in the main system is still detected.

    Common mistakes

    Warning

    A watchdog whose timer shares the failing clock cannot detect that clock failing. Safety-related designs use a separate low-frequency oscillator for the watchdog.

    Interview

    Follow-ups cover software disable protection, window watchdogs, and what resets the watchdog. The answers involve protected enable bits and independent clocks.

    Check yourself With TIMEOUT = 16, how many cycles after the last kick does timeout rise, and why does the counter compare against TIMEOUT−1?

    timeout rises 16 clock cycles after the kick. The counter is cleared to 0 by the kick and increments each cycle, so it reaches 15 (= TIMEOUT−1) after 15 cycles, and the 16th edge sets timeout. Comparing against TIMEOUT itself would make the interval one cycle too long.

    Testbench

    The bounded test checks kicking, exact firing time, disable clearing a partial interval, and sticky timeout under later kick and disable. Inputs are driven on falling edges; every rising-edge result is checked 1 ns after NBA updates, including every edge before and at timeout. Only reset clears a fired timeout.

    watchdog.sv
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    module watchdog #(parameter int TIMEOUT = 16) (   // TIMEOUT must be at least 1
      input  logic clk, rst_n,
      input  logic en,                        // watchdog enabled
      input  logic kick,                      // feed the dog
      output logic timeout                    // sticky: stays high until reset
    );
      // TIMEOUT = 1 guard ($clog2(1) is 0, so [$clog2(TIMEOUT)-1:0] would be [-1:0]).
      localparam int CW = (TIMEOUT > 1) ? $clog2(TIMEOUT) : 1;
      logic [CW-1:0] cnt;
      always_ff @(posedge clk or negedge rst_n)
        if (!rst_n) begin
          cnt     <= '0;
          timeout <= 1'b0;
        end else if (!en || kick) begin
          cnt <= '0;                          // a kick (or disable) restarts the interval
        end else if (cnt == TIMEOUT - 1) begin
          timeout <= 1'b1;                    // TIMEOUT cycles passed with no kick
        end else begin
          cnt <= cnt + 1'b1;
        end
    endmodule
    

    Remember

    • A kick or a disable clears the counter; TIMEOUT kick-free cycles set a sticky timeout.

    • Only reset clears a fired timeout.

    • A safety-related watchdog needs its own low-frequency clock source.

    Keep going

    • Code lab: Watchdog kick

    • Interview: run a mock interview on this topic

    Related topics

    • Counting as controlled state evolution

    • A Gray-code counter

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    See also

    • Counting as Controlled State Evolution
    • Up/Down Counter with Reload
    • Mini Project: a Programmable Timer
    clkkickcnt012012301timeout
    The page's watchdog with TIMEOUT = 4: a kick clears the count, four kick-free edges later timeout rises, and a later kick clears the count but not timeout