Somebody has to own the 70-clock descent into SLEEP and the 14.073 µs climb out, trusting the driver to quiesce the DMA before it asks, and timing out waits that never complete. On NanoSoC that somebody is the power sequencer inside nano_rstpwr, an always-on finite state machine with reset-controller handshakes on both ends. This topic reads it as an FSM, wires it to the reset tree, and sizes every timeout so the chip can neither hang nor hurry.
Lesson | After it you can... |
|---|---|
Walk every state, transition and output of the NanoSoC power sequencer. | |
Trace SW_OFF_REQ to switch, and pgood to reset release, across the two controllers. | |
Size each timeout, handle a block that refuses to quiesce, and never hang a sleep request. |
Suggested order: top to bottom. The FSM is the map, the handshakes are the borders with the reset controller, and the timeouts are what keeps both honest. Readers arriving from a wake failure should start at the handshake lesson and check RST_CAUSE first.
Because it has to act while PD_SW is dead: open the switch on entry and close it, wait out the ramp and relock the PLL on exit. Logic inside PD_SW cannot cause its own resurrection.