NanoSoC itself runs on one 0.9 V rail, but it lives on a board with several: IO, analogue and core supplies that must arrive in order, stay inside tolerance under load, and fail safely when they do not. The integrator owns that boundary: the rail order, the power-good checks that gate the cold-start timeline, the handshake with the power controller, and the response when a rail sags. This topic teaches the multi-rail view with NanoSoC as the single-rail degenerate case, and every multi-rail number in it is labelled illustrative.
Lesson | After it you can... |
|---|---|
Specify a rail order with thresholds and read the two-supply power-up waveform. | |
Wire the PMIC handshake and specify what a brown-out does to each domain. | |
Review decap, power-ground pairs and droop with the board team. |
Suggested order: top to bottom. Order first, because the handshake assumes it; handshake second, because brown-out is the handshake failing; board view last, because decap and droop are what make the first two true in silicon. The waveform in the first lesson is the section's only waveform: two rails ramping with power-good, POR and the ordered reset release.
Because the chip still plugs into a multi-rail board, and the power-good handshake it relies on is specified per rail. The single rail is the special case where the order collapses to one step; the method must still handle the general case the next chip will need.