The 82.74 mW RUN budget is a die number; the rail the die sees is a board number, shaped by bump resistance, plane inductance and the decap network between the regulator and the load. A chip that simulates clean and sags on the bench is usually a package-and-board miss, not a silicon miss. This lesson gives the integrator the review checklist for that boundary.
Delivery is reviewed in three layers. The bumps and balls carry the current: enough power and ground pairs that no pair exceeds its illustrative share, with pairs spread around the die so return paths stay short. The board planes and decap hold the rail during steps: bulk capacitance at the regulator, mid-frequency decap at the package, and on-die capacitance for the first nanoseconds, each covering the frequency band the next cannot reach. And the droop budget caps the total sag: the script below checks an illustrative 5 percent budget, 45 mV on the 0.9 V rail, against a resistive drop plus an inductive step for a worst-case load step of the whole 91.9 mA RUN current in 1.8 ns (50 A/µs), all illustrative except the 0.9 V nominal and the 82.74 mW RUN total that sizes the current.
# Droop budget check: resistive + inductive sag against 5% of 0.9 V.
# All impedances and the step size illustrative; rail and RUN power NanoSoC values.
V_NOM, BUDGET_FRAC = 0.9, 0.05
budget_mv = V_NOM * BUDGET_FRAC * 1000.0
R_BOARD_MOHM, L_BOARD_NH, DI_DT_A_PER_US = 4.0, 0.2, 50.0
I_RUN_A = 82.74e-3 / 0.9 # ~91.9 mA from the RUN total at 0.9 V
v_resistive_mv = I_RUN_A * R_BOARD_MOHM
v_inductive_mv = L_BOARD_NH * DI_DT_A_PER_US # nH * A/us = mV
total_mv = v_resistive_mv + v_inductive_mv
assert abs(I_RUN_A * 1000.0 - 91.93) < 0.05, I_RUN_A
assert abs(I_RUN_A / (DI_DT_A_PER_US * 1e6) * 1e9 - 1.84) < 0.02 # step time in ns
assert total_mv < budget_mv, (total_mv, budget_mv)
# The same step through an eight-times larger loop inductance busts the budget.
assert v_resistive_mv + 8 * L_BOARD_NH * DI_DT_A_PER_US > budget_mv
print("PASS: RUN ~91.9 mA; sag %.2f mV resistive + %.1f mV step < 45 mV budget"
% (v_resistive_mv, v_inductive_mv))The bump map shows power-ground pair count and placement, signed with the board team, not assumed from the die side alone.
The decap plan names all three tiers with values and bands; no tier is trusted to cover another's band.
The droop check above, or its board-team equivalent, passes with margin at the worst load step the software can produce.
Correlate the bench against the model: measure the rail at the balls during the DMA-plus-SPI worst step and compare with the budgeted sag. If the bench sags more, the missing element is usually a decap tier that the layout moved too far from the balls, or a plane split the current was not told about. Fix the layout before touching thresholds; a brown-out threshold moved to accommodate a bad board just relocates the failure.
Between the die and the regulator: the bump assignment, the package planes and the board decap placement. Die IR and board droop are different checks with different owners; passing one says nothing about the other.