NanoSoC as documented runs at one point, 0.9 V with 192, 96 and 24 MHz clocks, and has no DVFS controller, no regulator interface and no second operating point: DVFS is an extension at chip level, taught here because any product built from it wants slower cheaper gears and a method for moving between them without crashing. DVFS is that method: a table of safe voltage-frequency points, an order for moving between them that is never inverted, and a clock switch that never glitches. This topic teaches the integration of that method; NanoSoC's single point is the table with one row, and every extra row in it is illustrative. The regulator dependence is flagged wherever it matters.
Lesson | After it you can... |
|---|---|
Order any voltage-frequency transition and review one for inversion. | |
Read an OPP table and switch clocks without glitching. | |
Name every DVFS failure, its symptom and its guard, and flag what the regulator must guarantee. |
Suggested order: top to bottom. Ordering is the rule everything else obeys, the operating-point table is where the rule is applied, and the failure lesson is what happens when it is not. For the energy economics behind DVFS see DVFS and the Energy-Delay Tradeoff; for the clock-mux mechanism see Glitch-Free Clock Mux.
Because it assumes everything before it: stable rails from the supply topic, a sequenced PLL from the cold-start topic, and a power controller that can order steps. DVFS replays the power-up ordering on a running chip, so it comes after the ordering is taught.