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Course contents

  • How to Use This Course
  • The NanoSoC Tour
  • Reading Path
  • SoC Glossary10
  • SoC Metrics Reference
  • SoC Cheatsheet
  • What SoC Integration Is12
  • Architecture and Budgets21
  • Memory Maps and Address Decode26
  • Interconnect and Bus Fabrics26
  • Clock and Reset Architecture24
  • Power Architecture21
    • Power Domains and States
      • Always On Versus Switchable
      • RUN, IDLE and SLEEP
      • What Is Retained and What It Costs
    • Isolation and Retention Integration
    • PMU and Power Sequencer
    • Cold-Start Power-Up Sequence
    • Supply Sequencing and PMIC
    • Thermal and Power Envelope
    • DVFS Integration
  • Interrupts, DMA and Peripherals15
  • Memories, Boot and Security21
  • IP Integration and Handoff21
  • Top-Level Verification and Bring-up21
  • Package, Pads and I/O18
  • Chip Signoff and Tapeout18
  • SoC Interview Prep16
  • Capstone: Integrate NanoSoC14
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←Power Architecture
  1. Topics
  2. SoC Design
  3. Power Architecture
  4. Power Domains and States

Part 6 of 14Part 6 of 14/Power ArchitectureAll levels

Power Domains and States

PD_AON and PD_SW, the RUN, IDLE and SLEEP table, what is retained, and who owns each transition.

  • 3topics
  • 3lessons

NanoSoC has two power domains and three states, and every power bug the course teaches is a violation of the small contract between them: the switchable domain holds the compute, the always-on domain holds the wake logic, and the three states say exactly what is on, what is clocked and what survives. This topic places every block, costs every state in milliwatts from the NanoSoC power table, and shows what retention really buys. For the low-power vocabulary underneath see Power Domain Basics and Supply Sets and Power States.

Lesson

After it you can...

Always On Versus Switchable

Place every NanoSoC block in PD_AON or PD_SW and justify each placement.

RUN, IDLE and SLEEP

Read the state table and recompute the 82.74, 16.89 and 1.40 mW totals.

What Is Retained and What It Costs

Say what survives SLEEP, price retention leakage, and choose retention versus re-initialisation.

Suggested order: top to bottom. The domain split explains why the states exist, the state table is the contract software relies on, and retention is the detail that makes SLEEP useful instead of merely off. The isolation topic next door implements the boundary drawn here.

Check yourself Which domain holds the interrupt controller, and why must it?

PD_AON: a wake source in the switchable domain would lose power with everything else, and the chip could never wake. Wake logic always lives in the always-on island.

Expect to place blocks into two domains on a whiteboard and defend the two hardest calls: the SRAM0 wrapper logic, and the APB bridge sitting wholly in PD_SW although its far side talks only to always-on peripherals.

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See also

  • Isolation and Retention Integration
  • PMU and Power Sequencer
  • Cold-Start Power-Up Sequence