Cold start is the longest chain of trust on the chip: the supply must settle before POR releases, the crystal must run before the PLL locks, the PLL must lock before clocks open, the fabric must leave reset before the CPU, and the CPU must find the ROM before it finds anything else. Break any link and the symptom is a dead board with no diagnostic output. This topic strings the whole chain into one timeline with the NanoSoC numbers, so a dead board can be bisected link by link.
Lesson | After it you can... |
|---|---|
Recompute the 53.948 µs hardware timeline and name what each step waits for. | |
Price the oscillator and lock waits and handle lock that never comes. | |
Split the 12.581 ms boot total and say what dominates and why. |
Suggested order: top to bottom. The timeline is the spine, the crystal and PLL lesson prices its two longest waits, and the boot lesson shows why the hardware sequence, for all its care, is half a percent of the total. For the reset-ordering mechanism see Power-On and Warm Reset.
The crystal and POR steps: probe the crystal for oscillation and POR for release before touching anything digital. No clock means no lock, no resets and no ROM, so every later step is noise until the first two pass.