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Course contents

  • How to Use This Course
  • The NanoSoC Tour
  • Reading Path
  • SoC Glossary10
  • SoC Metrics Reference
  • SoC Cheatsheet
  • What SoC Integration Is12
  • Architecture and Budgets21
  • Memory Maps and Address Decode26
  • Interconnect and Bus Fabrics26
  • Clock and Reset Architecture24
  • Power Architecture21
    • Power Domains and States
    • Isolation and Retention Integration
      • Where the 114 Clamps Go
      • Enable Timing and the Safe Sequence
      • UPF Intent and What the Integrator Owns
    • PMU and Power Sequencer
    • Cold-Start Power-Up Sequence
    • Supply Sequencing and PMIC
    • Thermal and Power Envelope
    • DVFS Integration
  • Interrupts, DMA and Peripherals15
  • Memories, Boot and Security21
  • IP Integration and Handoff21
  • Top-Level Verification and Bring-up21
  • Package, Pads and I/O18
  • Chip Signoff and Tapeout18
  • SoC Interview Prep16
  • Capstone: Integrate NanoSoC14
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←Power Architecture
  1. Topics
  2. SoC Design
  3. Power Architecture
  4. Isolation and Retention Integration

Part 6 of 14Part 6 of 14/Power ArchitectureAll levels

Isolation and Retention Integration

Where the 114 clamps go, when they switch, how retention saves and restores, and the integration view of UPF intent.

  • 3topics
  • 3lessons

Every wire from the switchable domain into the always-on domain is a wire that will one day float, and the always-on logic downstream will read that float as something. Isolation is the set of clamps that decide what that something is, and retention is the companion decision about what comes back afterwards. NanoSoC needs exactly 114 clamps in four groups, asserted in a strict order around reset and the switch, and this topic counts them, times them and shows the intent that generates them. For the cell-level mechanism see Isolation Strategies; this topic teaches the integration view the course owns.

Lesson

After it you can...

Where the 114 Clamps Go

List every PD_SW to PD_AON signal group and prove the 114 total.

Enable Timing and the Safe Sequence

Order isolate, reset and switch, and review a sequence for the one inversion that breaks it.

UPF Intent and What the Integrator Owns

Read the UPF intent for NanoSoC and name what the integrator checks versus what the tools generate.

Suggested order: top to bottom. Count the clamps first, because the timing lesson enables exactly that set; then learn the order, because UPF intent is just this order written in a standard form. Readers debugging a sleep-wake loop should start at the second lesson.

Check yourself Why is isolation direction-specific, PD_SW into PD_AON only?

Because only powered-off outputs float. Signals from PD_AON into PD_SW drive into dead logic, which wastes nothing and corrupts nothing that survives; the 114 count covers the floating direction only.

Expect to be given the block list and asked for the clamp count. Walk the four groups, 47 plus 52 plus 13 plus 2, and say the clamp value and the enable name before giving the total.

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See also

  • Power Domains and States
  • PMU and Power Sequencer
  • Cold-Start Power-Up Sequence