Isolation cells with the right polarity still glitch the always-on domain if they switch at the wrong moment: enable isolation after the switch opens and a floating window leaks through; release it before the rails and PLL settle and the on-domain samples powered-but-reset values. On NanoSoC the whole order fits in 70 peripheral clocks going down and a longer climb coming up, and this lesson is that order with the cycle counts attached.
Power-down runs quiesce, isolate, reset, switch. Software first drains the DMA and the stream bridge and writes SW_OFF_REQ; the sequencer asserts iso_sw_en over 2 peripheral clocks, gates the clocks over 2 more, asserts both resets over 2 more, and only then opens the switch with a 64-cycle ramp, 70 peripheral clocks or 2.917 µs in total. Power-up inverts it: close the switch with the same 64-cycle ramp, wait 8 clocks past power-good, relock the PLL over 256 clocks, open the clocks, keep the resets asserted, release isolation 4 system clocks later, then release rst_sys_n after 18 system clocks and rst_cpu_n after 8 system clocks plus 2 CPU clocks. Isolation before reset before power off on the way down; power, then clocks, then isolation release, then reset release on the way up.
# not-run: NanoSoC sleep-entry and wake-exit order, NanoSoC teaching values
DOWN (70 clk_per = 2.917 us): quiesce DMA+SBR, SW_OFF_REQ
-> iso_sw_en assert (2 clk_per) -> clocks gated (2) -> resets asserted (2)
-> switch opens, ramp 64 clk_per. ISOLATION BEFORE RESET BEFORE OFF.
UP (14,073 ns): switch closes, ramp 64 clk_per -> pgood + 8 clk_per
-> PLL relock 256 clk_per -> clocks open + 2 clk_per -> resets held
-> isolation released (4 clk_sys later) -> rst_sys_n (18 clk_sys)
-> rst_cpu_n (8 clk_sys + 2 clk_cpu). POWER, CLOCKS, ISOLATION RELEASE, RESET RELEASE.# not-run: rush current of the switch ramp, illustrative charge values
PD_SW rail capacitance: illustrative 400 pF. Turning PD_SW on charges it.
In 2.667 us (the 64-clk_per ramp): I = 400 pF x 0.9 V / 2.667 us = 0.135 mA.
In a few nanoseconds (a single switch step): orders of magnitude more, and
the board rail sags. Hence a daisy-chained, staged turn-on (see
Low Power: Rush Current Mitigation), with pgood after the final stage.The wrapper below is the cell the integrator actually instantiates at the boundary: a plain AND clamp to zero. The enable iso_sw_en is registered once in the always-on sequencer, never in each cell and never from logic inside PD_SW: at cold power the sequencer resets with the enable asserted, so every boundary starts isolated until PD_SW is known-good. Real libraries provide these cells with no flops.
// NanoSoC teaching value: clamp-to-0 isolation (plain AND cell).
// iso_sw_en is registered once in the PD_AON sequencer; complete module.
module nano_iso_clamp0 (
input logic iso_en_aon,
input logic sig_sw,
output logic sig_aon
);
assign sig_aon = sig_sw & ~iso_en_aon;
endmoduleThe sequence diagram shows isolate before reset before switch on entry and the inverse on exit, with the NanoSoC cycle counts.
The isolation enable is registered once in the PD_AON sequencer; no enable is generated inside PD_SW, and at cold power the design starts isolated.
The wake path releases isolation only after power-good plus margin, never on the raw switch acknowledge.
Assert the order in power-aware simulation with sequence properties: releasing isolation while the rail or the PLL is not yet stable fails; releasing it while the resets are still asserted is the NanoSoC order and is expected, not a violation. If SLEEP entry glitches the interrupt controller, capture iso_sw_en against the reset control: the inversion is reset first, where reset assertion and then the collapsing rail can glitch the bridge outputs while the clamp is still transparent, and the interrupt controller sees it. Assert isolation first and the glitch disappears.
The release lands before the rails and the PLL are stable, so PD_AON samples settling values through transparent clamps. Wait for power-good plus the 8-clock margin and the relock before any release; acknowledge means the switch moved, not that the rail is usable.