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Course contents

  • How to Use This Course
  • The NanoSoC Tour
  • Reading Path
  • SoC Glossary10
  • SoC Metrics Reference
  • SoC Cheatsheet
  • What SoC Integration Is12
  • Architecture and Budgets21
  • Memory Maps and Address Decode26
  • Interconnect and Bus Fabrics26
  • Clock and Reset Architecture24
  • Power Architecture21
    • Power Domains and States
    • Isolation and Retention Integration
    • PMU and Power Sequencer
    • Cold-Start Power-Up Sequence
    • Supply Sequencing and PMIC
    • Thermal and Power Envelope
      • From Milliwatts to Degrees
      • Throttling Policy and Sensors
      • Power-Gating Saving and Break-Even
    • DVFS Integration
  • Interrupts, DMA and Peripherals15
  • Memories, Boot and Security21
  • IP Integration and Handoff21
  • Top-Level Verification and Bring-up21
  • Package, Pads and I/O18
  • Chip Signoff and Tapeout18
  • SoC Interview Prep16
  • Capstone: Integrate NanoSoC14
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←Power Architecture
  1. Topics
  2. SoC Design
  3. Power Architecture
  4. Thermal and Power Envelope

Part 6 of 14Part 6 of 14/Power ArchitectureAll levels

Thermal and Power Envelope

From milliwatts to degrees: the NanoSoC thermal path, throttling policy, sensors and power-gating break-even.

  • 3topics
  • 3lessons

82.74 mW does not sound like heat until it sits under a plastic package on a warm board with no airflow: power becomes temperature through one multiplication, and temperature decides how long the chip may sustain RUN before it must throttle. This topic turns the NanoSoC power table into a junction temperature, writes the throttling policy that keeps it inside the limit, and prices the sleep decision that avoids the heat entirely. Every thermal resistance and ambient in it is illustrative and listed as such.

Lesson

After it you can...

From Milliwatts to Degrees

Compute NanoSoC junction temperature from the power table and an illustrative package model.

Throttling Policy and Sensors

Write a sensor-trip throttling policy with hysteresis and recovery.

Power-Gating Saving and Break-Even

Price a sleep interval and find the nap length where SLEEP beats IDLE.

Suggested order: top to bottom. Temperature first, because the policy protects a number; policy second, because break-even decides how often the chip sleeps instead of throttling. Readers sizing a product enclosure start here and work backwards into the power table.

Check yourself Why does thermal management belong in the power section rather than packaging?

Because the lever is power: throttling, gating and DVFS all act on milliwatts, while the package only sets the resistance between those milliwatts and the ambient. The integrator owns both sides of the multiplication.

Expect to convert a power budget to a temperature on a whiteboard. Memorise the NanoSoC chain: 82.74 mW times an illustrative 30 °C/W plus ambient, and say which factor you would attack first.

PreviousNext: From Milliwatts to Degrees

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See also

  • Power Domains and States
  • Isolation and Retention Integration
  • PMU and Power Sequencer