A product team plans a sealed enclosure at 55 °C ambient, runs NanoSoC in sustained RUN at 82.74 mW, and discovers in testing that the margin they assumed was air. Every thermal surprise is this arithmetic done late: power times thermal resistance plus ambient, checked against the maximum junction temperature. This lesson does it early with the NanoSoC numbers.
Junction temperature is ambient plus power times the junction-to-ambient thermal resistance, and NanoSoC's power is small enough that almost any package passes. With an illustrative 30 °C/W package and 40 °C ambient, RUN lands at 42.5 °C, IDLE at 40.5 °C and SLEEP barely above ambient: rises of 2.5, 0.5 and 0.04 °C respectively. The lesson is not that NanoSoC runs cool, it is the method: the power column comes from the NanoSoC power table, the resistance and ambient are illustrative inputs the product owns, and the comparison against the limit decides whether throttling or gating is even needed. Change the ambient to a sealed 55 °C box and the answers move by 15 °C while the method stays identical.
# Junction temperature from the NanoSoC power totals.
# Powers NanoSoC teaching values; THETA_JA and AMBIENT illustrative.
P = {"RUN": 82.74e-3, "IDLE": 16.89e-3, "SLEEP": 1.40e-3} # watts
THETA_JA, AMBIENT, T_J_MAX = 30.0, 40.0, 105.0 # C/W, C, C (illustrative)
tj = {s: AMBIENT + p * THETA_JA for s, p in P.items()}
assert abs(tj["RUN"] - 42.482) < 0.01, tj
assert abs(tj["IDLE"] - 40.507) < 0.01
assert abs(tj["SLEEP"] - 40.042) < 0.01
margin = T_J_MAX - tj["RUN"]
assert margin > 60.0, margin # NanoSoC is thermally trivial in this package
# Sealed-box check: ambient 55 C still leaves over 47 C of margin.
assert T_J_MAX - (55.0 + P["RUN"] * THETA_JA) > 47.0
print("PASS: Tj RUN 42.5 C, IDLE 40.5 C, SLEEP 40.0 C; margin >60 C at 40 C ambient")The temperature computation names its three inputs with sources: NanoSoC power, product ambient, package resistance.
The worst sustained workload, not the average, feeds the RUN column; duty-cycled workloads carry their duty assumption.
The margin against the maximum junction temperature is stated per state, with the sealed-box ambient as a second case.
Correlate the model with a sensor reading under a sustained DMA workload: the measured rise over ambient divided by 82.74 mW is the effective resistance, and if it exceeds the assumed 30 °C/W the package model or the airflow assumption is wrong. If the chip throttles in the lab but the arithmetic says it should not, the workload is not the budgeted one: profile the actual switching before touching the thermal inputs.
Nothing structural: every junction temperature rises by exactly 15 °C and the margins shrink, but NanoSoC still clears the limit by over 47 °C. The policy trips stay where they are; only the recorded margin changes.