The wiring table says where each interrupt goes; this topic says when it gets there and what goes wrong on the way. One level travels from the DMA register block, through an isolation clamp and two synchronisers, into the CPU, and that journey is bounded between 135.4 and 182.3 ns. This topic walks the path stage by stage, turns the bound into a deadline calculator, and collects the three ways interrupts go missing or multiply: lost across a clock domain, lost in a clear-versus-set race, and storms from a level that was never cleared. For ordering against data see Interrupt and Data Ordering.

Suggested order: top to bottom. Walk the path first with the waveform beside you, then price it with the calculator, then study the failure signatures, which all assume you know what the healthy path looks like. The DMA topic next door (DMA Integration) produces the irq this topic carries.