Every interrupt on NanoSoC is a promise between a block and software: the source holds a level until software clears the cause, and the controller decides which waiting source the CPU hears about first. This topic builds that contract piece by piece: why levels won over pulses here, how the fixed-priority mask and TOP register work, and what the wiring review checks before any software runs. For the generic delivery models see Interrupts and Notification; for the peripheral-side registers see Interrupts and Events.
Lesson | After it you can... |
|---|---|
Choose level signalling, get the polarity right, and bound what a synchroniser costs. | |
Program ENABLE and read PENDING and TOP to dispatch any combination of sources. | |
Review an interrupt wiring table and read the controller RTL. |
Suggested order: top to bottom. Signalling first, because a pulse in a level system is the most common wiring bug; then the programming model, which is what the driver touches; then the wiring review, which is what the integrator signs. The next topic (Interrupt Routing and Latency) follows one irq along the wires this topic draws.
An active-high level held until software clears the status, matching every other NanoSoC input. A one-cycle pulse can fall between synchroniser edges and be missed entirely; the level waits as long as the controller needs.