This lesson has one job: close the DMA story at both ends, the interrupt that announces completion and the clock gate that must respect it. The completion path is the happiest waveform in the section: last word in, DONE set, irq up, software clears, irq down. The gating path is the least happy hang in the section: software stops the DMA clock mid-job and the whole peripheral bus freezes, because a clockless DMA cannot answer the APB. Both end here so the driver rulebook is complete.
Completion is ordered by construction. The LEN-th accepted word sets m_tlast, clears BUSY and sets DONE at the same edge (busy is high for four accepted beats and falls on the edge where done and irq rise), so irq rises, when IRQ_EN is on, in the same cycle the last output beat first appears. There is no gap for software to miss and no second event to collect: one DONE per job, held until cleared. Software answers with a write-1-to-clear of DONE, and exactly as the storm lesson warns, the clear is complete only when the level drops, so the handler reads STATUS back before returning. Clearing IRQ_EN also drops irq, but that mutes every future job too; the disciplined path clears the status, never the enable.
The waveform below is simulation output for the wave source of this topic: a four-word job completing, the irq rising with the last beat, and software clearing it. One slot is one clk_sys cycle at the 10 ns teaching period. The DATA-carrying lanes are 2-bit counters, shown for shape rather than value.
How to read it: busy rises in slot 1 when GO is written and is high for slots 1 to 3, falling in slot 4. The count lane steps 0, 1, 2, 3 over slots 0 to 3, one step per accepted word. The last lane is high for one slot (slot 3), the slot in which the fourth word is being accepted. In the next slot (slot 4) busy falls and DONE and irq rise together, irq tracking DONE because IRQ_EN is on; there is no pipeline tail after that. The clr strobe is high in slot 10, the software W1C write, and DONE and irq fall together one slot later. If irq rose but DONE never set, the job errored instead of completing; if DONE set but irq never rose, IRQ_EN was cleared by a careless CTRL write.
The DMA clock is gated by the CLK_EN bit in the reset controller, and the gate is glitch-free, so the electrical switching is safe. The protocol consequence is not: with its clock stopped the DMA cannot drive PREADY, and without further protection a CPU access to any DMA register would wait forever and the bus would appear hung. Two defences share the duty. The bridge carries a 256-cycle watchdog that completes a stranded access with PSLVERR, turning a silent hang into a loud error. And the clock control is specified to hold off gating while BUSY is set, so a gate request during a live job waits for the job to complete; the review checks that this hold-off exists in the controller or, at minimum, that software is proven to poll BUSY first. Software still follows the order: quiesce the DMA, confirm BUSY is 0, then clear the clock enable; re-enable the clock before touching any register.
# not-run: NanoSoC teaching values
Watchdog: 256 clk_sys cycles x 10.417 ns = 2.667 us to PSLVERR.
Gate order: poll BUSY = 0, then clear CLK_EN.DMA; reverse on wake.
A gated DMA answers nothing: without the watchdog the access hangs forever.The driver clears DONE and ERR together and reads STATUS back before returning from the handler.
Clock-gate sequencing is BUSY-aware: the control holds the gate off while BUSY, and software polls BUSY first regardless.
The bridge watchdog exists, its 256-cycle value is documented, and a test proves a gated-block access returns an error instead of hanging.
Replay the waveform scenario on the bench: start a 4-word job, watch DONE and irq rise together, clear with 0x6, watch irq fall. Then run the hostile version: clear CLK_EN mid-job and confirm the watchdog fires PSLVERR instead of hanging, and that gating while BUSY is held off or refused. If the CPU hangs on the first DMA access after a power-mode change, the clock enable is the first register to check: with the clock stopped, even a read of STATUS cannot complete.
The 0x6 rule: DONE was cleared but the sticky ERR from the earlier early-tlast job was left set, still holding irq. Always clear both bits after any job, and read STATUS back to confirm the level dropped.