Every protocol in a UVM testbench gets the same box: an agent with a sequencer, a driver and a monitor, configured from outside and connected to the pins through an interface. This topic takes that box apart using the DMA bench's two real agents, apb_agent and axis_agent, so every claim is backed by code that runs.
Name the three public surfaces of an agent (sequencer, analysis port, configuration) and explain why the env never reaches past them.
Configure an agent with knobs or a config object, and say who creates it and who wins when two components set it.
Write the mode-gated build that makes one agent class serve as an active driver at block level and a passive observer at chip level.
Write a protocol-correct driver and a monitor that publishes a fresh transaction per transfer, and explain the clock-edge timing behind both.
Choose between a virtual interface and an abstract BFM, and defend the choice for an emulation-friendly bench.
# | Lesson | What it answers |
|---|---|---|
1 | The block diagram, the three public surfaces, and why | |
2 | Knobs versus config objects, who creates them, and the shared-handle trap. | |
3 | How one class builds active or passive, | |
4 | Owning the pins: the APB waveform, reset parking, hooks, and the vanished write. | |
5 | Recognising a completed transfer and publishing a fresh object to every subscriber. | |
6 | The agent's stimulus socket, when to write your own, and the passive agent's missing one. | |
7 | Clocking blocks, | |
8 | Virtual interfaces, parameterized interface typing, and the abstract-BFM pattern. |
Read them in order the first time: each lesson's "What breaks" section sets up the next one's problem. If you only have twenty minutes before an interview, read lessons 1, 4 and 7.