Every arrow in the DMA bench is a TLM 1 connection. Three monitors publish on analysis ports, each agent hands its monitor's port up to the env, the scoreboard receives three streams through three imps, and each driver pulls items from its sequencer through a port and an imp. This topic explains each of those links well enough to wire a new one without guessing, to predict what the library reports when one is wrong, and to choose between the patterns senior reviewers argue about.
Name the port, export and imp on any link by asking who calls and who implements, and connect them in the legal direction.
Pick blocking, non-blocking or transport calls for a flow-controlled path, and know which ones consume time.
Explain analysis broadcast exactly: zero-time write(), fan-out and fan-in, and a subscriber order you must not rely on.
Predict which unconnected ports fail at end of elaboration, and use the built-in FIFOs and channels.
Choose between an imp_decl scoreboard and an analysis-FIFO scoreboard, and triage a transaction that went missing.
Lesson | What you learn |
|---|---|
Port, export and imp defined by the call, on the bench's monitor and driver links, and the subscriber that heard nothing. | |
Which way each link points, the agent's | |
Blocking and non-blocking calls, peek versus get, transport, and the zero-time spin. | |
One | |
min/max connection counts, resolve_bindings errors, | |
The bench's scoreboard rebuilt on analysis FIFOs, run side by side, and what each design costs at end of test. | |
A playbook for a missing transaction, occupancy-based depth sizing and loss policies. | |
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