Answer each question out loud before opening it. If you miss more than three in the checkpoint, revisit the lessons linked at the end.
A reference, a comparison on every output, end-of-test checks, a watchdog, one machine-readable verdict, and evidence the checks can fail.
Both: assertions for relations and timing where they apply, failing at the cause; scoreboards for results end to end against a reference.
Predict from accepted inputs, match each output against the oldest prediction of its ordering domain, and fail on leftovers at the end.
Usually not: match the specification's depth, and add timing only for rules about time, judged only where it is observable.
Key the scoreboard by the ordering domain the specification promises (flow, ID, address).
An end-of-test check: drain with a limit, then require every prediction to have been matched.
Show it was triggered (cover or count) and that it can fail (planted bug or mutation), and validate it on the clean design across many seeds.
Specify bounds; timestamp transactions; check tails under the relevant load; report separately from functional failures.
Task. A DMA engine reads descriptors, copies buffers from source to destination memory, and raises an interrupt per descriptor. Design its checking: which rules go to assertions, what the scoreboard predicts and how it matches, what is checked at the end, and how you would show each checker works.
Assertions (local, timing): bus protocol rules on both memory interfaces (valid held until ready, no X on control); interrupt is a pulse, or a level until cleared, as specified; no write to the destination outside the descriptor's range; busy status consistent with outstanding work. Scoreboard (end to end): predict from each descriptor accepted that destination memory will hold the source bytes; match by descriptor (descriptors may complete out of order if the engine has several channels, so key by channel or descriptor ID); check one interrupt per completed descriptor; check error status for injected bus errors. End of test: every descriptor completed and its interrupt seen; destination memory compared byte for byte; no extra writes anywhere (a memory model that records every write); status registers and counters read back. Proving the checks: plant faults in a copy of the design or a mutation campaign (an off-by-one length, a dropped interrupt, a wrong byte order) and confirm each is caught; cover the antecedents of the assertions; run the clean design on many seeds.
45 on the buggy FIFO; 0 on the correct one.
39,985 ns, about eleven times earlier.
They check rules whose violations the scoreboard already detected later; they detect earlier and more precisely.
The global-order scoreboard fails the legal run; the unordered (bag) scoreboard misses the swap.
Order within the same ID.
Six of fifteen.
That it was triggered, and that it fails when the design is wrong.
208 cycles against a 16-cycle bound.
It assumed packets were granted just before their first flit, but granted packets can wait for credits.
BUG_16 and BUG_23: no test clears PKT_CNT3 or disables a port, so they are never reached.