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Course contents

  • How to Use This Course
  • Reading Paths
  • Concept Map
  • Meet DCRouter
  • Glossary
  • Part 0: What Verification Is8
  • Part 1: What Can Go Wrong11
  • Part 2: Specifications as Checkable Rules8
  • Part 3: Observability and Controllability7
    • Controllability
    • Observability
    • Bug Propagation and Masking
    • Black Box, White Box, Grey Box
    • Hooks and Test Modes
    • Design for Verification
    • Drills: Observability and Controllability
  • Part 4: Stimulus11
  • Part 5: Checking11
  • Part 6: Coverage10
  • Part 7: Formal and Simulation10
  • Part 8: Verification Levels and Reuse8
  • Part 9: Planning and Risk9
  • Part 10: Emulation and Prototyping8
  • Part 11: Post-Silicon Validation8
  • Part 12: Bug Economics8
  • Part 13: Debug7
  • Part 14: Sign-Off7
  • Part 15: Verification in Context8
  • Part 16: Case Studies5
  • Part 17: Capstones5
  • Part 18: Interview Preparation6
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‹Part 3: Observability and Controllability
  1. Topics
  2. First Principles of Verification Strategy
  3. Part 3: Observability and Controllability
  4. Hooks and Test Modes

Part 3 · Observability and Controllability · Senior (S)

Hooks and Test Modes

Backdoors write or read state directly, test modes shorten timers and shrink limits, and internal monitors watch hidden signals. They buy controllability and observability cheaply, and each one skips something real. When each is worth it, what it hides, and how to keep at least one frontdoor path for everything a backdoor touches.

On this page

    Note

    Level: Senior (S) · Answers: Can we see and steer what matters?

    Before this: Controllability, Black Box, White Box, Grey Box

    To test that DCRouter's ERR_CNT1 saturates, lesson 4.7 sends 300 faulty packets: thousands of cycles to reach one boundary. A shortcut writes 254 straight into the counter through a hierarchical path, then sends two faulty packets. The test runs a hundred times faster. It also never exercises the increment logic that carried the counter from 0 to 254, and never checks that a counter at 254 is reachable the normal way.

    When should a test reach into the design instead of going through its pins?

    The obvious answer, and why it breaks

    The obvious answer is to use shortcuts whenever they save time: verification time is precious. But every shortcut replaces a real path with an artificial one. A backdoor write bypasses the logic that would have produced the value; a test mode with a shorter timer is not the mode that ships; a monitor that reads internal signals can fail to notice that the real outputs are wrong. Used without care, shortcuts verify a design that does not exist.

    The idea: three kinds of hook

    Hook

    What it does

    Power

    Danger

    Backdoor access

    Writes or reads state directly (register file, memory, counter) by hierarchical path or a register-model backdoor

    Reaches deep states instantly; loads memories in zero time; reads state with no bus traffic

    Skips the real write and read paths, their decoding, side effects and timing

    Test mode

    A configuration that shortens timers, shrinks limits, or exposes internal state on pins

    Makes rare events common; shortens tests

    The shipped mode is not the tested mode; mode-select logic itself can be wrong

    Internal monitor

    Watches internal signals to report or check events

    Observability of hidden state; precise debug

    Tied to the implementation; may be trusted instead of checking outputs

    A backdoor on DCRouter

    DCRouter's ERR_CNT registers can be read and cleared over APB but not written. A test can still preload one through the simulator's deposit interface (here UVM's uvm_hdl_deposit, in a UVM environment; without UVM, the simulator's VPI vpi_put_value or a vendor deposit command does the same, as does a register-model backdoor). It must not simply assign the signal from the testbench: a variable driven by an always_ff may not be written by any other process, and a write at the clock edge would race the design's own update.

    design.sv
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    // snippet: preload ERR_CNT1 by backdoor, then reach saturation through the frontdoor
    wait_drain();                                          // input 1 idle: nothing else updates err_cnt[1]
    void'(uvm_hdl_deposit("tb.dut.err_cnt[1]", 254));     // backdoor deposit: skips 254 increments
    queue_pkt(1, 0, 0, 2, 1);                      // two faulty packets through the real path
    queue_pkt(1, 0, 0, 2, 1);
    wait_drain();
    check_reg(8'h14, 255, "ERR_CNT1 saturates at 255");

    The saturation boundary (254 to 255 to 255) is still exercised by real faulty packets; only the climb from 0 is skipped. That is the safe pattern: backdoor to set up, frontdoor to test the behaviour under check. The climb itself still needs a frontdoor test somewhere, which lesson 4.7's 300-packet loop provides.

    Rules for using hooks safely

    • One frontdoor path for everything a backdoor touches: every register written by backdoor is also written and read through the bus at least once.

    • Backdoor for setup, frontdoor for the check: the behaviour a test claims to verify goes through the real path.

    • Test modes run beside the real mode: a shortened timer is tested, and the full-length timer is tested at least once, perhaps by formal.

    • Monitors add to output checks, never replace them: an internal event seen is not an output proven right.

    • Check the hook itself: test-mode select and debug logic ship in silicon and can be wrong.

    How real teams use hooks

    Practice

    Purpose

    Register-model backdoors for fast setup and mirror checks

    Load configuration quickly; compare the model's mirror with the design

    Memory preload by backdoor

    Load programs and data tables without simulating the load

    Shortened timers under a test parameter

    Make timeouts and watchdogs reachable in simulation

    A frontdoor test per register and per memory

    Covers the paths the backdoors skip

    What breaks

    A team (illustrative) configured every register by backdoor in all tests, for speed. The register block's address decoder had two registers swapped. No test ever wrote a register through the bus, so the swap was found by the first software bring-up in the lab. A single frontdoor write-and-read test of each register would have found it on the first day.

    Why this matters

    Senior lens. Treat every hook as a deliberate trade: name what it skips and where the skipped path is verified instead. A verification plan should list backdoors and test modes explicitly, with the frontdoor test or proof that covers each. Shortcuts are fine; unaccounted shortcuts are where escapes come from.

    Interview

    Asked: "When is a backdoor access a bad idea?"

    Weak answer: Never, it saves simulation time.

    Strong answer: When it replaces the thing you're trying to verify. A backdoor skips the real path: address decoding, bus protocol, side effects like clear-on-read, and the logic that would have produced the value. It's good for setup, like preloading memory or putting a counter near its limit, as long as the behaviour under test still goes through the frontdoor and every register a backdoor touches also has at least one real bus test. Configuring everything by backdoor is how swapped addresses reach the lab.

    Follow-ups: (1) What does a test mode risk? (2) How would you test a 32-bit timeout in simulation?

    Check yourself A test preloads ERR_CNT1 with 254 by backdoor and sends two faulty packets. What does it verify, and what does it skip?

    It verifies saturation at 255 through real faulty packets; it skips the counter's climb from 0 to 254, which another frontdoor test must cover.

    Check yourself Why must a shortened-timer test mode be accompanied by another test?

    The shipped configuration uses the full timer; its length, comparison and mode-select logic are not exercised by the shortened mode.

    Key takeaways

    • Backdoors, test modes and internal monitors buy controllability and observability cheaply.

    • Each one skips a real path: use hooks for setup and the frontdoor for the behaviour under check.

    • List every hook in the plan with the frontdoor test or proof that covers what it skips.

    Keep going

    Next: Lesson 3.6, Design for Verification. What designers can build in to make verification cheaper.

    Related topics

    • Part 3 overview: Observability and Controllability

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    See also

    • Controllability
    • Observability
    • Bug Propagation and Masking