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Course contents

  • How to Use This Course
  • Reading Paths
  • Concept Map
  • Meet DCRouter
  • Glossary
  • Part 0: What Verification Is8
  • Part 1: What Can Go Wrong11
  • Part 2: Specifications as Checkable Rules8
    • Intent and the Oracle
    • From Prose to Rules
    • Reference Models
    • Tables and Executable Specifications
    • Specification Review and Ambiguity
    • Requirements Traceability
    • What Not to Check
    • Drills: Specifications as Checkable Rules
  • Part 3: Observability and Controllability7
  • Part 4: Stimulus11
  • Part 5: Checking11
  • Part 6: Coverage10
  • Part 7: Formal and Simulation10
  • Part 8: Verification Levels and Reuse8
  • Part 9: Planning and Risk9
  • Part 10: Emulation and Prototyping8
  • Part 11: Post-Silicon Validation8
  • Part 12: Bug Economics8
  • Part 13: Debug7
  • Part 14: Sign-Off7
  • Part 15: Verification in Context8
  • Part 16: Case Studies5
  • Part 17: Capstones5
  • Part 18: Interview Preparation6
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‹Part 2: Specifications as Checkable Rules
  1. Topics
  2. First Principles of Verification Strategy
  3. Part 2: Specifications as Checkable Rules
  4. What Not to Check

Part 2 · Specifications as Checkable Rules · Principal (P)

What Not to Check

A check that forbids behaviour the specification allows is a bug in the testbench: it fails legal designs, wastes debug time and pressures designers into matching the testbench instead of the specification. Where over-specified checks come from, and how to check exactly what is promised.

On this page

    Note

    Level: Principal (P) · Answers: What exactly are we checking against?

    Before this: Reference Models

    A designer improves DCRouter's arbiter so that a waiting packet is granted one cycle earlier. Nothing in the specification changes. Overnight, three hundred tests fail. The scoreboard expected packets from input 2 before those from input 3 at output 0, because that was the order the old arbiter happened to produce. The design got better and the testbench called it broken.

    What should a check not check, and why does over-checking matter?

    The obvious answer, and why it breaks

    The obvious instinct is "the stricter the better": check every output against exactly what the design produced in a known-good run, cycle for cycle. But a check stricter than the specification forbids behaviour the specification allows. It fails legal designs, buries real failures among false ones, and quietly turns the testbench into the specification, so designers learn to match the testbench rather than the document.

    The idea: check what is promised, and nothing more

    Over-specified check

    What the specification actually promises

    Check instead

    Exact output order across inputs

    Order within each flow only

    Match per (input, output) flow (lesson 2.3)

    Exact latency of 7 cycles

    Latency at most 10 cycles

    A bound: response within 10 cycles

    A specific value on don't-care bits

    Bits are reserved or undefined

    Mask them out

    The exact cycle a counter updates

    Updated before it is read

    Check the value when read

    Internal signal values

    Behaviour at the pins

    Check at the interface unless the rule is internal

    Results of a golden run

    Results allowed by the rules

    A model of the rules, not a recording

    design.sv
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    // snippet: two ways to check DCRouter's output order
    // bad-example idea (in words): "packets from input 2 leave output 0 before packets from input 3"
    // That order is the arbiter's choice; the specification does not promise it.
    
    // Right: within one flow (same input and output), order is promised. A scoreboard keeps one
    // queue per flow and compares each arriving packet with the oldest expected packet of its flow:
    //   expected[src][dst].pop_front() must equal the packet that arrived from src at dst.

    The per-flow scoreboard accepts every legal interleaving at an output and still catches the bugs that matter: a lost, duplicated, corrupted or misordered packet within a flow.

    Where over-checking comes from

    • Recording instead of modelling: comparing with the output of a past run captures its accidents as requirements.

    • Cycle-accurate models where results were specified (lesson 2.3).

    • Checking internals: assertions on internal signals encode one implementation.

    • Filling ambiguity with the design's behaviour: the RTL's choice becomes a rule nobody wrote (lesson 2.5).

    Over-checking versus under-checking

    Too strict

    Too loose

    False failures on legal designs

    Missed real bugs

    Wasted debug time, eroded trust in failures

    False confidence

    Designers optimise for the testbench

    The specification is not enforced

    Both are verification bugs. The target is a check that fails exactly when a rule is broken.

    How real teams avoid it

    Practice

    Purpose

    Scoreboards matching per ordering domain (ID, flow)

    Accept every legal reordering

    Latency checked as bounds

    Allow implementation freedom within the specification

    Checker reviews against the specification

    Find rules the testbench invented

    Mutation of legal behaviour

    Changing the design legally should not fail tests

    What breaks

    The opening arbiter improvement (illustrative) cost the team three days of triage before someone noticed every failure was an ordering difference across inputs. Replacing the recorded-order comparison with a per-flow scoreboard made all 300 tests pass again; it also, within a week, caught a genuine misordering within one flow that the recorded comparison had been masking among its false alarms.

    Why this matters

    Principal lens. Treat every check as a claim about the specification and ask, for each, which rule it enforces. A check that cannot cite a rule is either enforcing an undocumented requirement, which should be written into the specification, or an implementation accident, which should be removed. Testbenches that check exactly the promises keep their failures meaningful.

    Interview

    Asked: "Can a checker be too strict?"

    Weak answer: No, stricter checking finds more bugs.

    Strong answer: Yes. A check stricter than the spec forbids legal behaviour: it fails correct designs, buries real failures in false ones, and makes the testbench the de facto spec. Typical cases are checking order across independent streams when only per-stream order is promised, exact latencies where the spec gives a bound, don't-care bits, internal signals, or comparing with a recorded golden run. I check exactly what's promised: per-flow ordering, latency bounds, masked reserved fields, behaviour at the pins, and I make every check cite the rule it enforces.

    Follow-ups: (1) How do you check a latency requirement properly? (2) What do you do with a check that can't cite a rule?

    Check yourself A scoreboard compares DCRouter's output 0 stream with a recording from last week, flit by flit. What legal change would break it?

    Any change to arbitration timing that interleaves packets from different inputs in a different order, which the specification allows.

    Check yourself The specification says "a response within 10 cycles". The check asserts "exactly 7 cycles". What happens when a designer adds a pipeline stage?

    Every test fails with latency 8, although 8 meets the specification; the check should assert a bound of 10.

    Key takeaways

    • A check stricter than the specification is a testbench bug: it fails legal designs.

    • Check exactly what is promised: per-flow order, latency bounds, masked don't-cares, behaviour at the pins.

    • Every check should cite the rule it enforces.

    Keep going

    Next: Drills: Specifications as Checkable Rules. Interview questions, a whiteboard exercise and a ten-question checkpoint for Part 2.

    Related topics

    • Part 2 overview: Specifications as Checkable Rules

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    See also

    • Intent and the Oracle
    • From Prose to Rules
    • Reference Models