Answer each question out loud before opening it. If you miss more than three in the checkpoint, revisit the lessons linked at the end.
Chip simulation is slow, control and visibility are poor, and failures are hard to localise; find each bug at the lowest level that can see it.
Hit, miss, replacement and state logic at block level (with formal); coherence between caches at subsystem level; coherence with DMA and software, and performance on workloads, at chip level or in emulation.
Assertions, monitors, monitor-fed scoreboards, coverage models and register models; drivers are replaced by real neighbours.
For an independent model of a standard interface, with drivers, protocol checkers, coverage and compliance tests; your own model shares your designers' reading.
Address maps, configuration sequences across blocks, end-to-end data flows, interrupts, power and reset sequencing, and boot.
Run the real driver against a virtual platform, RTL simulation and emulation, with one register specification generated for both sides.
Static or formal checks of isolation and level shifting, and power-aware simulation that corrupts switched-off domains, plus sequencing and power-management software tests.
Task. An SoC has two processor cores with caches, a coherent interconnect, a DMA engine, a DDR controller with a bought PHY, an Ethernet MAC and a power controller that switches off the MAC's domain when the link is down. Assign the main features to levels, name what you would reuse upward, which VIP you would buy, and three chip-level software tests.
Block: each cache's hit, miss, eviction and state machine (with formal); the interconnect's arbitration, ordering and deadlock freedom (formal plus random); the DMA's descriptor handling and error paths; the MAC's frame handling against Ethernet VIP; the DDR controller's scheduling against DDR memory models. Subsystem: coherence between the two caches and the interconnect, including snoops colliding with fills; DMA and caches sharing memory. Chip: address map and register access from the cores; boot; DMA to MAC data flows; interrupts; the power controller switching the MAC domain off and on with power-aware simulation, isolation and retention checked; performance of a network workload. Reuse upward: interface assertions and protocol checkers on every bus, monitor-fed scoreboards for the interconnect and DMA, coverage models, register models. Buy: Ethernet VIP, DDR memory models and PHY models, AXI VIP for the interconnect's ports. Chip software tests: boot and memory test through the caches; DMA copy with cache maintenance and completion interrupts; link down, MAC domain power-off, link up, driver restore, traffic resumes.
Block level, at DCRouter's own pins.
It is a disagreement between two real blocks, each tested against a model of the other.
They check connections, interactions, software and performance, not the block corners already closed lower down.
Assertions written on the design's own pins; in DCRouter's case most of dcr_sva.svh (the R13 timing assertion needs rework), while the formal properties travel with the RTL but run only in formal.
It must decode destination and expected error from the monitored flits instead of taking them from its driver's record.
Your own interface model shares your designers' reading of the standard, so shared misreadings pass every test.
A software-driven chip-level test running on the processor.
For example, a driver expecting one write to clear all four error counters, when R9 clears only the one written.
IEEE 1801 (UPF).
The bugs are in functional sleep logic; isolation only matters when a domain is switched off, which only power-aware simulation models.