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Mixed-Signal Physical Verification

Mixed-Signal Integration: Mixed-signal PV combines digital and analog rule decks, LVS partition assumptions, and waiver discipline to achieve manufacturable signoff.

What this topic teaches

Mixed-Signal Physical Verification converts analog-digital assumptions into a measurable engineering contract. Mixed-signal PV combines digital and analog rule decks, LVS partition assumptions, and waiver discipline to achieve manufacturable signoff. The hard part is proving which boundary broke first, under which mode, and with which evidence.

The senior-engineer question

When AMS PV closure rate, signoff waiver count, rerun turnaround moves, can you isolate the first failing boundary, identify owner, and define the smallest reversible change that proves root cause?

diagram
AMS CLOSURE FLOW — Mixed-Signal Physical Verification

spec + handoff assumptions
        |
        v
boundary implementation (wrapper/cells/reset)
        |
        v
physical context (floorplan/power/package)
        |
        v
metrics + artifacts (jitter/BER/noise/validity)
        |
        v
root-cause classification -> bounded fix -> regression

Debug rule: always name mode, boundary, evidence tag, and owner.

Picture the boundary behavior

Start every study session by drawing the contract before opening logs or reports. The diagrams below are what to reproduce on whiteboard.

Mixed-signal PV closure

diagram
DRC + LVS + ERC + analog-specific checks
          -> waiver review
          -> AMS release gate

Boundary sequence

diagram
AMS BOUNDARY SEQUENCE — Mixed-Signal Physical Verification

analog macro -> wrapper / boundary cell -> synchronizer or sampler -> digital consumer
      |                 |                         |                     |
  analog assumptions    legal voltage/state       clock/reset contract   protocol/data validity

metric under watch: AMS PV closure rate, signoff waiver count, rerun turnaround

Who owns which layer

diagram
AMS OWNERSHIP LAYERS — Mixed-Signal Physical Verification

layer                owns                                failure mode
------------------   ----------------------------------  --------------------------
spec contract         clocks/resets/interfaces            hidden assumption drift
wrapper logic         synchronizers/framing/flags         silent data corruption
physical integration  floorplan/isolation/power           coupled noise and droop
signoff governance    waivers/checklists/dashboard        release with blind spots
closure               debug order + regression            fix regresses another mode

Evidence to collect

  • Primary metric: AMS PV closure rate, signoff waiver count, rerun turnaround.

  • Primary artifact: PV signoff dashboard, LVS mismatch summary, waiver approvals.

  • Owners to bring into review: PV lead, analog layout owner, program signoff owner.

  • One tagged reproduction and one reduced reproducer.

  • Cross-check from at least two evidence planes: functional and physical/signoff.

Ownership map

diagram
OWNERSHIP MAP — Mixed-Signal Physical Verification

artifact                  owner
----------------------    -----------------------------
integration artifact    PV lead
implementation artifact analog layout owner
signoff artifact        program signoff owner

Every boundary issue needs a named owner before fixes start.

Subpages in this topic

Each topic includes mechanism, contract I/O, reports, debug, worked example, pitfalls, interview, checklist, theory, design-space, extended case study, walkthrough, comparison matrix, software view, and silicon PPA impact.

Key takeaways

  • Carry boundary and mode context with every metric.

  • Prove mechanism with tagged evidence before changing silicon-facing logic.

  • Close with explicit owner-aligned regression criteria.

Common pitfalls

  • Assuming lock/ready/valid means healthy behavior.

  • Ignoring package and power contributors in jitter/SerDes issues.

  • Waivers without expiry, owner, or mitigation plan.

AMS deep dive

Physical proximity and boundary rules are functional constraints in AMS SoCs.

Concept diagram

diagram
INTEGRATION FLOW

floorplan keepouts -> guard strategy -> abutment policy -> PV signoff

Metric graph

diagram
INTEGRATION ESCAPES

layout boundary issues ███████
waiver drift           ████

Reports and artifacts

  • keepout violations

  • guard-ring checks

  • abutment DRC

  • mixed-signal PV dashboard

Mini case study

Late macro move violated quiet-zone assumptions and caused intermittent converter noise excursions.

Debug branches

  • Review macro adjacency

  • Re-check guard assumptions

  • Re-run PV with correct deck variant

Senior review question

Ask: what boundary condition proves this topic is actually closed?

Key takeaways

  • State boundary, mode, and evidence tag with every claim.

  • Always align analog, digital, and physical owners before signoff decisions.

Common pitfalls

  • Fixing averages while tails still fail.

  • Skipping package/supply evidence in jitter or SerDes issues.

  • Shipping with waivers that lack owner and expiration criteria.