Foundational theory

Mixed-Signal Physical Verification is central to Mixed-Signal Integration. Mixed-signal PV combines digital and analog rule decks, LVS partition assumptions, and waiver discipline to achieve manufacturable signoff. Senior AMS owners always tie observed failure to boundary assumptions, ownership, and measurable evidence before changing RTL or layout.

Core concepts explained

• Mixed-signal PV combines digital and analog rule decks, LVS partition assumptions, and waiver discipline to achieve manufacturable signoff.

• Primary metric: AMS PV closure rate, signoff waiver count, rerun turnaround

• Primary artifact: PV signoff dashboard, LVS mismatch summary, waiver approvals

• Owners: PV lead, analog layout owner, program signoff owner

• Boundary and mode context are mandatory for any claim.

• Treat lock/ready/valid bits as evidence, not proof of health.

Why this matters at signoff

At tapeout and bring-up, Mixed-Signal Physical Verification escapes are expensive to fix. Floorplan and physical boundaries are part of the functional contract. Wrong diagnosis burns schedule across analog, digital, and package teams.

Mental model

DRC + LVS + ERC + analog-specific checks
          -> waiver review
          -> AMS release gate

Worked intuition

1. Name boundary and product mode where failure appears.

2. Open AMS PV closure rate, signoff waiver count, rerun turnaround and identify worst scenario.

3. Trace clocks/resets/config from analog macro to digital consumer.

4. Verify wrapper and handoff assumptions on the failing path.

5. Collect PV signoff dashboard, LVS mismatch summary, waiver approvals and freeze evidence tags.

6. Classify root cause: contract gap, physical coupling, sequencing bug, or tool-view mismatch.

7. Propose minimal bounded change plus cross-domain regression.

Common misconceptions

• Lock high means clock quality is automatically good.

• Boundary cells are one-time checklist items, not runtime risks.

• SerDes training failure is always firmware.

• If average metric is healthy, there is no silicon risk.

Visual reinforcement

Mixed-signal PV closure

DRC + LVS + ERC + analog-specific checks
          -> waiver review
          -> AMS release gate

Layer responsibilities

AMS OWNERSHIP LAYERS — Mixed-Signal Physical Verification

layer                owns                                failure mode
------------------   ----------------------------------  --------------------------
spec contract         clocks/resets/interfaces            hidden assumption drift
wrapper logic         synchronizers/framing/flags         silent data corruption
physical integration  floorplan/isolation/power           coupled noise and droop
signoff governance    waivers/checklists/dashboard        release with blind spots
closure               debug order + regression            fix regresses another mode

AMS deep dive

Physical proximity and boundary rules are functional constraints in AMS SoCs.

Concept diagram

INTEGRATION FLOW

floorplan keepouts -> guard strategy -> abutment policy -> PV signoff

Metric graph

INTEGRATION ESCAPES

layout boundary issues ███████
waiver drift           ████

Reports and artifacts

• keepout violations

• guard-ring checks

• abutment DRC

• mixed-signal PV dashboard

Mini case study

Late macro move violated quiet-zone assumptions and caused intermittent converter noise excursions.

Debug branches

• Review macro adjacency

• Re-check guard assumptions

• Re-run PV with correct deck variant

Senior review question

Ask: what boundary condition proves this topic is actually closed?

Key takeaways

• State boundary, mode, and evidence tag with every claim.

• Always align analog, digital, and physical owners before signoff decisions.

Common pitfalls

• Fixing averages while tails still fail.

• Skipping package/supply evidence in jitter or SerDes issues.

• Shipping with waivers that lack owner and expiration criteria.

Theory reinforcement

Floorplan and physical boundaries are part of the functional contract.