A clock domain boundary is where one timing assumption ends and synchronisation begins. Put the cut where the data is naturally slow, narrow, or already packetised, and each crossing stays cheap. Cut through fast, wide, tightly coupled logic and every crossing becomes a project.
Every crossing pays some combination of the following. The table uses illustrative cycle counts for a two-flop synchroniser: 2 to 3 destination cycles of latency per crossing.
Cost | What it looks like |
|---|---|
Latency | 2 to 3 destination cycles per synchroniser stage crossing; a handshake round trip adds the acknowledge path as well. |
Throughput limit | A pulse needs spacing of several destination cycles; a handshake moves one item per round trip. |
Area | Synchroniser flops, handshake state machines, or a FIFO per crossing. |
Verification | One more item in structural analysis, one more protocol to assert, one more row in the inventory. |
Constraints | Each clock pair needs its crossing intent captured; each synchroniser needs its preservation attributes. |
Keep feedback loops inside one domain. A request-acknowledge pair that crosses twice (there and back) already spans two synchroniser delays; do not add a third cut inside the loop.
Group logic by rate, not by function. A fast data path and its slow control register do not belong in the same domain just because they serve one feature.
Cut where the data is already slow. Configuration, status, and packet boundaries cross far more cheaply than cycle-by-cycle data.
Do not split a pipeline across domains. A pipeline stage boundary looks like a natural cut but carries wide data every cycle; it needs a FIFO, not a synchroniser.
Treat muxed and gated clocks as boundaries. A clock mux output and a gated clock each create a domain relationship the partition must name (see the clock gating and muxing topic).
The reviewer asks for the domain diagram and counts the crossings on it. A design with three domains and four documented crossings is easy to sign off; a design with three domains and forty scattered signals is not, whatever the synchronisers look like.
Twelve separate crossings where one would do: the wires are related control, so they should cross as one defined protocol (a handshake or a qualified register), and the cut should sit at that single protocol, not across twelve ad-hoc signals.