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Course contents

  • How to Use This Course
  • PD Flow Overview — RTL to GDSII
  • Data & Libraries — What PD Receives
  • Data and Libraries49
  • Floorplanning Expanded65
  • Power Planning57
  • Placement65
  • Clock Tree Synthesis57
  • Routing65
  • Timing Closure81
  • Signal Integrity and Variation41
  • Power Signoff57
  • Physical Verification65
  • Physical Design Integration49
    • DFT Physical Implementation
    • Scan Chain Physical Effects
    • Bump Map and Package Interface
    • ESD and IO Ring Integration
    • Chip-Level Assembly Flow
    • IP Block Abstract Integration
      • IP Block Abstract Integration — Mechanism
      • IP Block Abstract Integration — Inputs & Outputs
      • IP Block Abstract Integration — Reports & Metrics
      • IP Block Abstract Integration — Debug Playbook
      • IP Block Abstract Integration — Worked Example
      • IP Block Abstract Integration — Pitfalls & Red Flags
      • IP Block Abstract Integration — Interview Drills
      • IP Block Abstract Integration — Review Checklist
    • Physical Design Integration Tricky Q&A
  • Signoff and Tapeout49
  • PD Interview Prep5
  • PD Closure Cheat Sheet
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