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Course contents

  • How to Use This Course
  • The NanoSoC Tour
  • Reading Path
  • SoC Glossary10
  • SoC Metrics Reference
  • SoC Cheatsheet
  • What SoC Integration Is12
  • Architecture and Budgets21
  • Memory Maps and Address Decode26
  • Interconnect and Bus Fabrics26
  • Clock and Reset Architecture24
  • Power Architecture21
  • Interrupts, DMA and Peripherals15
  • Memories, Boot and Security21
  • IP Integration and Handoff21
  • Top-Level Verification and Bring-up21
  • Package, Pads and I/O18
  • Chip Signoff and Tapeout18
    • The Signoff Manifest
    • Waiver Governance
    • Closure Dashboards
    • Tapeout Readiness Review
    • ECO and Respin Risk
      • Metal-Only Against Full Respin
      • Late ECO Discipline
      • Spare Cells
    • Errata and Post-Silicon
  • SoC Interview Prep16
  • Capstone: Integrate NanoSoC14
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←ECO and Respin Risk
  1. Topics
  2. SoC Design
  3. Chip Signoff and Tapeout
  4. ECO and Respin Risk
  5. Metal-Only Against Full Respin
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    Part 12 of 14, lesson 13 of 18Part 12 of 14/Chip Signoff and Tapeout/Lesson 13 of 18All levels

    Metal-Only Against Full Respin

    Cost thinking in weeks and risk: what a metal-only fix can touch, what forces a respin, and the arithmetic.

    Why it matters

    The most expensive sentence in signoff is that a fix is small so it must be cheap. A one-gate logic change can force an all-layer change if no spare gate sits where the signal can reach, while a hundred-gate change in a spare-rich block fixes in metal. Cost follows what layers must change and what must be re-verified, not the size of the diff. This lesson prices the paths in engineering weeks, mask and fab time, and residual risk. Its one job is the comparison; the process around it is next.

    The core idea

    A metal-only ECO changes a subset of the metal and via layers, often including low layers where the spare cells sit, and leaves every base layer untouched. Wafers can sometimes be held at an earlier stage and only the changed masks remade. It can fix miswiring, wrong tie-offs, inverted polarity and small logic errors, provided spare cells exist within reach and timing still closes. An all-layer ECO changes base layers: it needs the full mask set but reuses most of the implementation database, so it is the middle option when a fix needs new cells or new placement but not a new design. A full respin repeats synthesis, implementation and signoff: it is forced by any change the other two cannot absorb, such as a map, interface or power-intent change.

    Cost has two parts. Engineering effort, in weeks, is the model below. External cost and time, the mask set, the fab cycle time and the wafer-lot lead time, usually dominates the calendar on real chips and is shown here as a share of the mask layers remade and a fab time. Every figure is a NanoSoC teaching value in illustrative weeks or layers, not a quote. A schedule-risk allowance is shown beside the effort, never inside it.

    example.py
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    # Price the three paths. All figures are illustrative NanoSoC
    # teaching values (engineering weeks, mask layers out of an assumed 40,
    # fab weeks); they are not vendor or foundry data.
    effort = {
        "metal": {"edit": 2, "eco-timing": 3, "equivalence": 3,
                  "focused-regression": 7},
        "all-layer": {"edit": 2, "eco-timing": 4, "equivalence": 3,
                      "focused-regression": 7, "re-signoff": 14},
        "respin": {"resynthesis": 4, "place-route": 12, "full-signoff": 22,
                   "full-regression": 22},
    }
    mask_layers = {"metal": 6, "all-layer": 40, "respin": 40}
    fab_weeks = {"metal": 6, "all-layer": 12, "respin": 12}
    risk_allowance = {"metal": 3, "all-layer": 6, "respin": 12}  # separate
    
    bill = {p: sum(items.values()) for p, items in effort.items()}
    assert bill == {"metal": 15, "all-layer": 30, "respin": 60}, bill
    assert bill["respin"] / bill["metal"] == 4.0
    calendar = {p: bill[p] + fab_weeks[p] for p in bill}   # effort, then fab
    assert calendar == {"metal": 21, "all-layer": 42, "respin": 72}, calendar
    assert mask_layers["metal"] < mask_layers["respin"]
    
    def path(c):
        """Route a change to the cheapest path that can absorb it."""
        if c.get("map") or c.get("power_intent") or c.get("interface"):
            return "respin"
        if c.get("needs_new_cells") and not c.get("spare_reach"):
            return "all-layer"
        if not c.get("timing_closes", True):
            return "all-layer"
        return "metal"
    
    assert path({}) == "metal"                                   # re-route (the interrupt miswire)
    assert path({"needs_new_cells": True, "spare_reach": True}) == "metal"
    assert path({"needs_new_cells": True, "spare_reach": False}) == "all-layer"
    assert path({"timing_closes": False}) == "all-layer"
    assert path({"map": True}) == "respin"
    assert path({"power_intent": True, "needs_new_cells": True,
                 "spare_reach": True}) == "respin"
    print("PASS: effort 15 / 30 / 60 weeks, calendar 21 / 42 / 72, five routes checked")

    What the review looks for

    • The ECO request states which path it takes and why the other path cannot: spare reach for metal, re-verification scope for respin.

    • The bill in effort weeks, mask layers and fab weeks is attached with the same line items as above, so two ECOs can be compared.

    • A map, interface or power-intent change is never priced as metal-only.

    Verify and debug

    Check the path claim against the spare map: the miswired signal must physically reach a spare cell of the right kind with timing to spare, confirmed by the implementation owner, not assumed by the requester. If the reach fails, the ECO reprices to an all-layer change or a respin immediately, before any editing starts; discovering it after the edit wastes both the edit and the week.

    Diagram
    # not-run: the path test, NanoSoC teaching values (illustrative)
    metal-only if: spare of right kind within reach (or a pure re-route)
      AND timing closes AND no map, interface or power-intent change
    all-layer  if: new cells or placement needed, no spare in reach
    respin     if: map, interface or power-intent change
    effort 15 / 30 / 60 weeks; calendar 21 / 42 / 72 with fab time

    Pricing only the engineering effort. The Respin vs Metal-Fix Decision Criteria lesson weighs silicon-fix options and software workarounds alongside the silicon paths, and mask and fab time often decide the calendar. An erratum with a driver workaround at 3 weeks beats a metal fix at 15 whenever the workaround truly contains the bug, which is the errata topic's question.

    If asked to choose between a metal fix and a respin for a miswired interrupt, answer metal, because it is a re-route, with the three checks: the wires reachable in metal, timing closure, equivalence on the cone. Then name what flips it: a change that needs a cell with no spare in reach becomes an all-layer change, and a map or power-intent change becomes a respin, decided before lunch, not after a wasted week of editing.

    Check yourself A one-line RTL change fixes the bug but needs a new state bit. Metal or respin?

    Not metal-only unless a spare flop with the right clock and reset sits within reach and the cone re-verifies; without one it is an all-layer change, since a new cell needs base layers. The diff size is irrelevant; the new state is what prices it.

    Related topics

    • Next: Late ECO Discipline

    • Physical Design: Post-Mask ECO Flow

    • Bring-Up: Respin vs Metal-Fix Decision Criteria

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    See also

    • Spare Cells