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Course contents

  • How to Use This Course
  • The NanoSoC Tour
  • Reading Path
  • SoC Glossary10
  • SoC Metrics Reference
  • SoC Cheatsheet
  • What SoC Integration Is12
  • Architecture and Budgets21
  • Memory Maps and Address Decode26
  • Interconnect and Bus Fabrics26
  • Clock and Reset Architecture24
  • Power Architecture21
  • Interrupts, DMA and Peripherals15
  • Memories, Boot and Security21
  • IP Integration and Handoff21
  • Top-Level Verification and Bring-up21
  • Package, Pads and I/O18
  • Chip Signoff and Tapeout18
    • The Signoff Manifest
    • Waiver Governance
      • What May Be Waived
      • Waiver Ageing
      • The Escape Rate
    • Closure Dashboards
    • Tapeout Readiness Review
    • ECO and Respin Risk
    • Errata and Post-Silicon
  • SoC Interview Prep16
  • Capstone: Integrate NanoSoC14
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←Waiver Governance
  1. Topics
  2. SoC Design
  3. Chip Signoff and Tapeout
  4. Waiver Governance
  5. The Escape Rate
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    Part 12 of 14, lesson 6 of 18Part 12 of 14/Chip Signoff and Tapeout/Lesson 6 of 18All levels

    The Escape Rate

    What a wrong waiver costs: escape arithmetic, the post-silicon price, and the bar for the next grant.

    Why it matters

    Granting a waiver is betting the chip that the violation does not matter. Most bets win, which is what makes the lost ones dangerous: the team learns that waivers are free, grants more of them, and eventually excuses the violation that kills the schedule. Escape arithmetic keeps the price visible by counting how often waived violations turned into silicon problems, and weighing those against everything the waivers saved. Its one job is the price tag; the dashboard that watches the count is next.

    The core idea

    The escape rate is the fraction of granted waivers that later caused a silicon issue, a respin, an erratum entry or a software workaround: escapes divided by grants over a window the project chooses, usually one chip. A rate of zero with few grants means discipline; a rate of zero over hundreds of grants usually means the checker is noisy, or that the escape mapping is not being done. The cost side multiplies each escape by what it took to contain it: an erratum with a software workaround is cheap, a metal-only fix is dear, a full respin dwarfs both, as the ECO topic prices. The weeks here are engineering effort only; mask and fab time come on top, as the ECO topic explains. The benefit side counts engineering weeks not spent chasing false violations. The bar for the next grant follows directly: a class with a nonzero escape rate needs stronger evidence or stops being waivable.

    example.py
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    # Escape-rate arithmetic over one chip window.
    # Counts are NanoSoC teaching values, not measurements.
    grants = {"false": 60, "proven-safe": 25, "bounded-risk": 8}
    escapes = {"false": 0, "proven-safe": 1, "bounded-risk": 1}
    # containment cost per escape in illustrative engineering weeks
    # (the same price table as the ECO topic; excludes mask and fab time)
    cost_weeks = {"erratum-workaround": 3, "metal-fix": 15, "respin": 60}
    escape_bill = [("proven-safe", "erratum-workaround"),
                   ("bounded-risk", "metal-fix")]
    
    total_grants = sum(grants.values())
    total_escapes = sum(escapes.values())
    rate = total_escapes / total_grants
    bill = sum(cost_weeks[c] for _, c in escape_bill)
    assert total_grants == 93
    assert total_escapes == 2
    assert abs(rate - 0.0215) < 0.001, rate
    assert bill == 18, bill
    for kind in grants:
        r = escapes[kind] / grants[kind]
        print(kind, "grants", grants[kind], "escapes", escapes[kind],
              "rate", round(r, 4))
    assert escapes["false"] == 0
    print("PASS: 93 grants, 2 escapes, rate 2.2 percent, bill 18 weeks")

    What the review looks for

    • The escape rate for the current chip is quoted with its window: grants, escapes and containment bill, not just the ratio.

    • Any class with an escape carries tightened evidence rules, written down before the next grant in that class.

    • The post-silicon waiver escapes, failures found in silicon that a waived check would have caught, are listed as errata inputs.

    Verify and debug

    Close the loop after silicon: for every post-silicon bug, ask whether a waived check covered it, and record the answer in the escape table whether or not it flatters the team. An escape table that stays empty while errata grow is not good news; it means the mapping is not being done. The errata topic owns that mapping.

    Blaming the checker after an escape (see Escape Analysis). The question is never whether the checker was noisy; it is whether the evidence attached to the waiver actually covered the escaped case. Fix the evidence bar, not the tool.

    If asked whether a 2 percent escape rate is good, answer that the rate alone says nothing: two escapes contained by errata are tuition, one escape needing a respin is a disaster. Quote the bill in weeks alongside the rate (18 engineering weeks here, mask and fab time excluded), and say what changed in the granting bar.

    Check yourself Bounded-risk grants show one escape contained by a metal fix. What changes tomorrow?

    The bounded-risk bar tightens: the integrator co-signs with fresh containment analysis, or the class stops being waivable for paths without a software workaround. The escape buys a rule, not just a story.

    Related topics

    • Waiver Ageing

    • Next: Closure Dashboards

    • Verification: Residual Risk

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    See also

    • What May Be Waived