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Course contents

  • How to Use This Course
  • The NanoSoC Tour
  • Reading Path
  • SoC Glossary10
  • SoC Metrics Reference
  • SoC Cheatsheet
  • What SoC Integration Is12
  • Architecture and Budgets21
  • Memory Maps and Address Decode26
  • Interconnect and Bus Fabrics26
  • Clock and Reset Architecture24
  • Power Architecture21
  • Interrupts, DMA and Peripherals15
  • Memories, Boot and Security21
  • IP Integration and Handoff21
  • Top-Level Verification and Bring-up21
  • Package, Pads and I/O18
  • Chip Signoff and Tapeout18
  • SoC Interview Prep16
    • The Whiteboard Framework
    • Design a SoC on a Whiteboard
      • Requirements to a Timed Plan
      • NanoSoC as the Model Answer
      • Variations: Bandwidth, a Second DMA, a Secure Partition
    • Integration Storm and Budget War Scenarios
    • Rapid-Fire Questions by Section
    • Numeric Drills
  • Capstone: Integrate NanoSoC14
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←Design a SoC on a Whiteboard
  1. Topics
  2. SoC Design
  3. SoC Interview Prep
  4. Design a SoC on a Whiteboard
  5. Variations: Bandwidth, a Second DMA, a Secure Partition
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    Part 13 of 14, lesson 6 of 16Part 13 of 14/Interview Prep/Lesson 6 of 16All levels

    Variations: Bandwidth, a Second DMA, a Secure Partition

    Three new requirements on the same spine: more bandwidth, a second DMA, and a secure partition, each with its price.

    Why it matters

    No interviewer accepts the model answer and stops; the real test is the variation. More bandwidth, another master, a security region: each forces one structural change, and the candidate who re-derives from the spine passes while the candidate who redraws from scratch runs out of time. This lesson works three variations with their prices, each as a margin note on the model answer rather than a new diagram.

    The core idea

    Variation one, double the stream bandwidth. The spine's limit is the shared bank: source and destination in the same SRAM halve each stream to 180.7 MB/s. The fix is placement, not logic: source in SRAM0, destination in SRAM1, each bank serving one direction at 361.4 MB/s. The price is a software contract, buffers allocated per direction per bank, plus a check that the allocator enforces it. If the requirement exceeds even that, the honest answer is a second bank or a wider fabric, priced as area and another arbitration port, not as a tweak.

    Variation two, a second DMA engine. The fabric grows from two masters to three: arbitration stays round robin but the idle-cycle cost on master change now hits three parties, outstanding limits and ID widths are recomputed, the interrupt table takes spare input 6, which ranks below every existing source, so a latency-critical second DMA would force a re-ranking, and the clock enables gain a second gate bit. The stream bridge question decides the shape: one shared bridge means the two DMAs contend for one read and one write engine, two bridges mean two full paths at twice the area. State the choice and its price; the interviewer is testing whether sharing is free, and it never is.

    Variation three, a secure partition for keys. The spine already has one: SRAM1 is secure-only and the interconnect and APB decoder enforce AxPROT. The variation extends it: the new key store joins the secure region, its filter sits at the slave so a misbehaving master cannot bypass it, and non-secure software touching it gets SLVERR. The honest answer also names the hole in NanoSoC as built: the stream bridge's NS attribute (CTRL bit 2) resets to non-secure but sits in a non-secure register slot, so non-secure software can clear it and make the bridge issue secure accesses. The partition is not closed until that bit is writable from the secure side only, or the slot moves to secure-only; say so before the interviewer finds it. The price is verification: a per-master reachability matrix proving each master reaches exactly its regions, plus directed tests that non-secure accesses fault, including a non-secure write to the bridge's NS bit. The script below prices the first two variations from the spine numbers; the fair-share lines are an illustrative model in which every burst pays its own bubble and each change of master pays one more idle clock.

    example.py
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    sustained = 4 * 96e6 * 16 / 17 / 1e6  # per-link sustained MB/s
    # Variation 1: split banks vs shared bank for a 2-direction stream job.
    split = 2 * sustained          # one direction per bank
    shared = sustained             # one bank serves both directions
    assert abs(split - 722.8) < 0.2 and abs(shared - 361.4) < 0.2
    # Variation 2: round-robin share per master with 1 idle cycle per change.
    # Illustrative teaching values: 16 beats + 1 bubble = 17 clocks per burst, plus 1 idle clock on a master change, fair rotation.
    burst_cycles, idle = 17, 1
    share_2 = burst_cycles / (2 * (burst_cycles + idle))
    share_3 = burst_cycles / (3 * (burst_cycles + idle))
    assert abs(share_2 - 0.4722) < 0.001 and abs(share_3 - 0.3148) < 0.001
    print(f"split banks {split:.1f} MB/s both directions; shared {shared:.1f} MB/s")
    print(f"fair share per master: 2 masters {share_2 * 100:.1f}%, 3 masters {share_3 * 100:.1f}%")
    print("PASS: placement doubles streaming; a third master costs a third of turns")

    What the review looks for

    • Each variation changes the spine minimally and names the price: a contract, area, a verification task.

    • Bandwidth claims state their conditions: per direction, per bank, shared or split.

    • The secure variation names where the filter sits and what the fault looks like to software.

    Verify and debug

    For each variation, write the one check that would catch its characteristic bug: an allocation test proving source and destination sit in different banks, a three-master stress test measuring each master's share against the fair fraction, a non-secure read of the secure region expecting SLVERR. If a variation has no check, it is a wish, and interviewers treat wishes as 2s.

    Security attribute dropped or attacker-controlled: a bridge or converter that does not propagate the non-secure sideband lets the wrong master through the firewall. The variation answer carries the sideband end to end, which is the sentence that earns the 4.

    Answer variations as deltas: what changes, what it costs, what checks it. Never redraw the whole chip; the margin note proves you own the spine.

    Check yourself The interviewer doubles bandwidth again after the split-bank fix. What now?

    The spine is exhausted: both banks at efficiency, fabric at 361.4 per link. Say so, then price the structural options: a second bank pair, a wider datapath, or a coherent cache for reuse, each with area and verification cost. Admitting the limit scores higher than inventing throughput.

    Related topics

    • NanoSoC as the Model Answer

    • SoC: Where the Filter Lives

    • SoC: QoS in Practice on NanoSoC

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    See also

    • Requirements to a Timed Plan