The design-a-chip question is the whole interview in one exercise: a one-line requirement, thirty minutes, and a marker. The candidate who draws boxes for twenty minutes and discovers the address map does not fit has failed; the candidate who budgets five minutes per subsystem and writes numbers beside every arrow passes. This topic gives the time plan, the full worked solution using NanoSoC as the model answer, and three variations that test whether the structure survives new requirements. It covers the memory-map, fabric, reset, clock and power questions in one pass.
Lesson | After it you can... |
|---|---|
Turn one line of requirements into a block diagram, a map sketch, a fabric choice and a clock plan in thirty minutes. | |
Walk a complete chip: diagram, map, fabric, clocks, resets, power, interrupts and boot, every step with a number. | |
Rework the model answer under three new requirements without redrawing the whole chip. |
Suggested order: top to bottom. Learn the plan first, because the plan is what you rehearse; then the model answer, which is what you memorise as numbers; then the variations, which are what the interviewer actually asks after the easy part. For the generic system-design method see System Design Questions.
Because decode widths, window sizes and slot counts size the fabric: the map decides how many slaves the fabric arbitrates and which accesses cross to the slow segment. Fabric before map means re-deriving the arbitration when the map changes.