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Course contents

  • How to Use This Course
  • The NanoSoC Tour
  • Reading Path
  • SoC Glossary10
  • SoC Metrics Reference
  • SoC Cheatsheet
  • What SoC Integration Is12
  • Architecture and Budgets21
  • Memory Maps and Address Decode26
  • Interconnect and Bus Fabrics26
  • Clock and Reset Architecture24
  • Power Architecture21
  • Interrupts, DMA and Peripherals15
  • Memories, Boot and Security21
    • Memory Subsystem Integration
    • ECC and Error Handling
    • External Memory Controller Integration
    • Boot ROM and Boot Modes
    • eFuse and OTP
      • What Lives in the Fuse Array
      • Read-Out Timing and Distribution
      • Repair, Lifecycle and Locking
    • Secure Boot and Root of Trust
    • Security Architecture
  • IP Integration and Handoff21
  • Top-Level Verification and Bring-up21
  • Package, Pads and I/O18
  • Chip Signoff and Tapeout18
  • SoC Interview Prep16
  • Capstone: Integrate NanoSoC14
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←Memories, Boot and Security
  1. Topics
  2. SoC Design
  3. Memories, Boot and Security
  4. eFuse and OTP

Part 8 of 14Part 8 of 14/Memories, Boot and SecurityAll levels

eFuse and OTP

What is stored in fuses, how read-out timing works, and the integration risks of one-time memory.

  • 3topics
  • 3lessons

Some bits must survive every reset, every sleep and every firmware update: oscillator trim, boot configuration, memory repair addresses and the device's secrets. NanoSoC keeps them in one-time-programmable fuses read once at reset into shadow registers. This topic teaches what lives in the array, when it is read and distributed, and the three integration risks that follow from memory that can never be erased. Fuse field allocations here are NanoSoC teaching values, because the NanoSoC reference table defines the need but not the map. These lessons carry the whole subject for the course.

Lesson

After it you can...

What Lives in the Fuse Array

Allocate fuse fields for trim, configuration, repair and secrets.

Read-Out Timing and Distribution

Sequence fuse read-out before first use and check every consumer.

Repair, Lifecycle and Locking

Route repair fuses to the SRAM wrappers and manage lifecycle states.

Suggested order: top to bottom. Allocate the fields first, because timing and routing both follow the allocation; then sequence the read-out; then connect repair and lifecycle. The secure-boot topic consumes the key and version fields defined here.

Check yourself Why do fuses get shadow registers instead of letting every block read the array directly?

Because the array is slow, power-hungry and readable only in a special mode. One sequenced read at reset copies each field into an ordinary flop near its consumer, and normal logic never touches the array again.

Expect to explain why a fuse is not just a ROM bit: it is written after manufacture on the tester, it cannot be erased, and its read path needs sequencing that ROM never does.

Related topics

  • Next: Secure Boot and Root of Trust

  • Bring-up: Secure Boot Enablement and Fuse Bring-up

PreviousNext: What Lives in the Fuse Array

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See also

  • Memory Subsystem Integration
  • ECC and Error Handling
  • External Memory Controller Integration