NanoSoC fits its whole world in two SRAM banks, which is exactly why it is the right chip to learn the next step on: nothing here is obscured by a real controller, so the integration contract stands out cleanly. When the software outgrows 128 KB, an external memory controller joins the fabric as a third slave, and the integrator owns everything around it: its clocks and resets, the calibration it needs before the first access, where its windows sit in the map, and how its reordering interacts with the rest of the chip. This topic teaches that contract at the integration level and points at the DRAM courses for mechanism. For controller and PHY structure see DDR Controller / PHY Split; for training detail see Training and Timing Modes.
Lesson | After it you can... |
|---|---|
List every clock, reset, calibration and address connection a controller needs. | |
Budget controller bandwidth against master demand and place ordering boundaries. | |
Say who owns each step from power-up to first access, and what software may assume. |
Suggested order: top to bottom. Wire it first, because the budgets assume the connections exist; then budget bandwidth and ordering; then sequence the bring-up that makes the first access legal. All controller numbers here are illustrative teaching values: NanoSoC ships without external memory, and the NanoSoC reference defines none of them.
Because the controller is a memory with a training sequence and a retention story, not just another slave. Its calibration, initialisation and error reporting are memory problems that happen to attach to the fabric.