This lesson has one job: name every wire the integrator is responsible for around a controller the team did not design. Controllers arrive as hardened blocks with a fabric port on one side and a PHY link on the other, and the space between the datasheet and a working chip is all integration: which clock drives the controller core, which reset releases it, where calibration results are stored, which address bits interleave across channels, and where QoS classes attach. Miss one and the symptom is a memory that trains on the bench and fails in the system.
The fabric port is an AXI4 slave like any other, sized to the controller's data width with its own clock domain and an asynchronous bridge if the controller runs faster than the 96 MHz fabric. The PHY link carries the calibrated interface to the pads; the integrator does not design the PHY but owns its reference clock, its reset, its power rail sequencing, and the board-level routing constraints the PHY dictates. Address mapping decides which bits select the channel, bank and row: interleaving consecutive cache lines across channels buys parallelism for sequential DMA traffic but scatters one stream across power-hungry pages, so the map is a workload decision. Ordering follows from the controller's rescheduling: reads may overtake writes to open pages, which is why a DMA completion interrupt must be ordered against its data, exactly the fence discipline the fabric section teaches. For the DRAM-side view see Address Mapping, Interleaving, and Disturb-Aware Placement and The Memory-Controller Boundary.
Interface | What the integrator provides | NanoSoC parallel |
|---|---|---|
Fabric port | AXI4 slave wiring, clock bridge, QoS class, secure filter entry | The SBR master port and the SRAM1 secure filter |
PHY and pads | Reference clock, reset, power sequencing, board routing rules | The crystal and pad reset debounce |
Calibration store | Where training results live across sleep and reset | SRAM0 retention (training results must live in retained or always-on storage) and RST_CAUSE (to choose train or restore) |
Address map | Controller windows in the map, interleave bits, reserved growth | The SRAM0/SRAM1 split and its banking rule |
Errors | Correctable counters and uncorrectable path into the error aggregator | The ECC reporting paths of the previous topic |
Each of the five interfaces names its owner, its clock and its reset; none is owned by implication.
The interleave bit choice is written down with the workload that justifies it, and the verification plan covers the opposite pattern.
The secure filter covers the controller windows exactly as it covers SRAM1: mapped but refused for the wrong state.
Check connectivity per bit from the fabric to the controller port and from the controller to the PHY before any traffic test: a dropped address bit aliases gigabytes, not kilobytes. Then run single-beat accesses to each interleave region and confirm they land on distinct channels. If sequential traffic piles onto one channel, the interleave bits are wired to the wrong address slice.
Separate them by channel or by bank: give the DMA stream its own channel (or bank group) so the CPU's random accesses close other pages, not the DMA's open one. The cost is that neither side can use the other's idle capacity, and interleaving the stream across channels would restore parallelism at the price of waking more pages. The choice is workload-driven, which is why the integrator documents the assumed traffic.