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Course contents

  • How to Use This Course
  • The NanoSoC Tour
  • Reading Path
  • SoC Glossary10
  • SoC Metrics Reference
  • SoC Cheatsheet
  • What SoC Integration Is12
  • Architecture and Budgets21
  • Memory Maps and Address Decode26
  • Interconnect and Bus Fabrics26
  • Clock and Reset Architecture24
  • Power Architecture21
  • Interrupts, DMA and Peripherals15
  • Memories, Boot and Security21
    • Memory Subsystem Integration
    • ECC and Error Handling
    • External Memory Controller Integration
      • What the Integrator Wires
      • Bandwidth and Ordering Budgets
      • Initialisation and Training Ownership
    • Boot ROM and Boot Modes
    • eFuse and OTP
    • Secure Boot and Root of Trust
    • Security Architecture
  • IP Integration and Handoff21
  • Top-Level Verification and Bring-up21
  • Package, Pads and I/O18
  • Chip Signoff and Tapeout18
  • SoC Interview Prep16
  • Capstone: Integrate NanoSoC14
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←External Memory Controller Integration
  1. Topics
  2. SoC Design
  3. Memories, Boot and Security
  4. External Memory Controller Integration
  5. Bandwidth and Ordering Budgets
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    Part 8 of 14, lesson 8 of 21Part 8 of 14/Memories, Boot and Security/Lesson 8 of 21All levels

    Bandwidth and Ordering Budgets

    Demand versus achievable bandwidth with efficiency, QoS classes per master, and where ordering is enforced.

    Why it matters

    This lesson has one job: prove the controller is big enough before it is bought. Peak datasheet bandwidth is never achieved: page misses, refresh, read-write turnarounds and arbitration shave a workload-dependent fraction off the top. The integrator's spreadsheet adds every master's worst-case demand, multiplies the peak by a realistic efficiency, and either closes the budget or rebalances traffic. An unbudgeted controller fails only under full-system load, which is the most expensive place to discover arithmetic.

    The core idea

    Usable bandwidth is peak times efficiency, and the efficiency range of 60 to 85 percent is workload-dependent, never a guarantee. Sequential bursts to open pages sit near the top; random traffic with constant page misses sits near the bottom. Each master gets a QoS class so a bulk DMA cannot starve a latency-critical reader, and the controller's scheduling policy belongs in the integration specification alongside the classes. Ordering completes the picture: the controller may reorder for efficiency, so software-visible order is restored with barriers and by checking interrupt-against-data paths, the same discipline the DMA lessons teach. For the scheduling view see QoS Classes, Priority Arbitration, and Starvation Boundaries; for the collapse scenario see Scenario: DDR Bandwidth Collapse.

    The worked example is a NanoSoC-style budget with illustrative controller numbers. Two masters demand 400 and 200 MB/s against a 900 MB/s peak at 70 percent efficiency, which closes with margin; raising the second master to 300 MB/s breaks it, and the script shows both outcomes so the re-budget habit is mechanical.

    example.py
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    peak = 900.0
    eff = 0.70
    usable = peak * eff
    assert abs(usable - 630.0) < 1e-9, usable
    for label, demands in (("closes", (400, 200)), ("breaks", (400, 300))):
        total = sum(demands)
        margin = usable - total
        print(f"{label}: demand {total} vs usable {usable:.0f}, margin {margin:+.0f} MB/s")
        assert (margin >= 0) == (label == "closes")
    print("PASS: budget closes at 600, breaks at 700 MB/s demand")

    What the review looks for

    • Every master that can reach the controller appears in the demand column with its worst case, not its average.

    • The efficiency number names the workload it assumes; a single efficiency for all workloads is a review finding.

    • QoS classes are assigned per master and checked in performance simulation with all masters active.

    Verify and debug

    Drive the traffic model with the budgeted mix and measure achieved bandwidth and tail latency at the controller port; then rerun with the starvation mix of bulk-plus-latency-critical and confirm the QoS classes hold. If throughput meets the budget but tails miss, the efficiency was right and the scheduling policy was wrong.

    Bandwidth oversubscription: summed worst-case demand exceeds achievable DRAM throughput. Symptom: missed throughput targets and latency tails that appear only with all masters active. Caught by the spreadsheet budget plus traffic-model simulation. Fix: re-budget, add caches, or compress; never tune the efficiency to fit.

    If asked whether a controller is big enough, answer with the inequality first: sum of worst-case demands against peak times a justified efficiency. Then say which workload justifies the efficiency you picked.

    Check yourself Two masters each demand half the usable bandwidth. Why can the system still miss its deadlines?

    Because bandwidth is an average and deadlines are about tails: without QoS classes one master bursts while the other waits, and the average still looks fine. Budget the classes, not just the bytes.

    Related topics

    • What the Integrator Wires

    • Next: Initialisation and Training Ownership

    • DRAM: QoS Classes, Priority Arbitration, and Starvation

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