This lesson has one job: assign every step between power-up and the first memory access to exactly one owner. A controller that answers before its PHY is calibrated returns garbage with a valid handshake; firmware that programs timing registers while traffic flows corrupts the calibration it stands on. The sequence crosses hardware, firmware and the power controller, which is why unowned gaps appear and why the first-access hang is the classic symptom.
The order is fixed: power rails ramp, the PHY reference clock stabilises, hardware or firmware runs training that centres each data eye and stores the delays, firmware programs the controller timing registers from the memory datasheet values and the saved training results, and only then does the fabric gate open for traffic. Training results must survive sleep, so they are saved to always-on registers or re-run at wake (fuses cannot hold them: fuse data is written once at the factory, while training results move with voltage and temperature; the reset-cause register tells the ROM whether to train or restore); the retention lesson's save-and-restore discipline applies bit for bit. Ownership splits three ways: the power controller owns rails and clocks, firmware owns the training firmware and register programming, and the controller hardware owns the gate that blocks traffic until training completes. For the firmware view see Firmware Initialization and DRAM Training Flow; for the controller theory see Row Buffers and Controller Scheduling.
# not-run: illustrative training budget, illustrative teaching values
Training sweep: 64 delay steps x 32 lines x 10 reads per step = 20,480 reads.
At 100 ns per read: about 2.05 ms, paid once per boot and once per wake.
First-access rule: no fabric transaction until the trained flag reads back set;
a single polling loop on that flag replaces every guess about timing.The sequence diagram names the owner of each step and the flag that proves the step finished.
Training results have a named home across sleep: retained registers or a documented re-train at wake.
No software path issues a memory access before the trained flag reads back set.
Simulate the sequence with the training engine modelled as a timed stub and confirm the traffic gate stays shut until the trained flag sets; then force the flag path low and confirm every early access errors instead of hanging. If the first access hangs rather than erroring, the gate is missing and the default-slave discipline of the decode section was not extended to the controller window.
Only when the delays are retained in always-on storage across sleep and the operating point is unchanged. If voltage or frequency changed, or the values were not retained, the shortcut corrupts traffic and the 2 ms must be paid.