Every NanoSoC wakes at address zero with cold caches, uninitialised memories and one job: reach running software in 12.581 milliseconds. The boot ROM does that job in sixteen modelled steps (one access in flight at a time), from the 53.948 microseconds of hardware reset to a 10.928 millisecond image load that dwarfs everything else. This topic teaches where the reset vector lives, how the ROM decides between a cold boot and a wake, what each microsecond costs, and how the ROM hands control to SRAM0. For the bring-up view see Boot ROM Execution and Firmware Stage Handoff; for reset sequencing see Reset Sequencing and Clock Tree Bring-up.

Suggested order: top to bottom. Place the vector and read the reset cause first, because every later step assumes address zero answers and knows which kind of boot this is; then cost the whole flow; then hand off to SRAM and plan for the ROM's mistakes. The fuse topic next door supplies the trim and configuration this flow reads.