Signoff vs Implementation Views: Software / Programmer View

RTL / implementation view

Mode-specific clock gating and power intent affect which scenarios matter.

What designers feel

• Surprise timing after RTL 'small' change

• Clock domain bugs

RTL structure impact

• Pipeline depth

• Reset and clock gating

• Boundary flop placement

Synthesis interaction

• Retiming constraints

• Don't care optimization vs STA

RTL-side mitigations

• Register boundaries

• Clean clocking

• Review SDC with RTL changes

RTL — Signoff vs Implementation Views
// pipeline stage added -> check new reg2reg path group WNS

Layer the driver touches

STA OWNERSHIP LAYERS — Signoff vs Implementation Views

layer              owns                         failure mode
----------------   --------------------------   ---------------------
constraints        clocks, IO, exceptions       false violations
implementation     cells, nets, placement       real path delay
extraction         SPEF/RC corners              view mismatch
signoff policy     derate, MMMC matrix          margin disputes
closure           ECO order, regression        fix breaks other corner

STA deep dive

Signoff WNS is the minimum across the full scenario matrix.

Concept diagram

MMMC

corners (ss/tt/ff) x modes (func/test) x views (signoff RC)
= scenario set -> min(WNS) is signoff

Metric graph

WNS HEATMAP BY CORNER

        ss    tt    ff
setup  -80   +10   +5
hold   -15   -2    -8

Reports and artifacts

• per-corner WNS

• mode summary

• lib map audit

• view delta

Mini case study

Passed TT typical but failed SS hold — signoff matrix was incomplete; added low-voltage mode.

Debug branches

• Isolate failing scenario first

• Never compare unlike SPEF tags

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

• State corner, mode, view, and database tag with every slack claim.

• Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

• Comparing STA runs with different SPEF or SDC tags.

• Broad false_path to green-wash violations.

• Setup-only ECO without hold check.

Principal STA review addendum

Implementation and signoff use different parasitic corners and analysis views; comparing them without mapping causes false panic or false confidence.

Metric: view delta WNS, parasitic corner mismatch, SPEF vs signoff RC gap