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Course contents

  • Logic Synthesis Glossary
  • Logic Synthesis Cheatsheet
  • Synthesis Foundations14
  • Logic Optimisation and Mapping20
  • Constraints and Timing15
  • Sequential, FSM and Memory19
  • Datapath Synthesis14
    • Adders and Carry Structures
    • Multipliers and Compressors
      • Partial Products and the Array Multiplier
      • Booth Radix-4 Recoding
      • Compressor Trees
      • Signed Multiplication and Sign Extension
      • Truncation, the Final Adder, and Equivalence
    • Resource Sharing and Arithmetic Inference
  • Area, Power and Test14
  • Verification, ECO and Handoff15
  • Flows and Debugging15
  • Interview and Judgment11
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‹Multipliers and Compressors
  1. Topics
  2. Logic Synthesis
  3. Datapath Synthesis
  4. Multipliers and Compressors
  5. Partial Products and the Array Multiplier

Part 5 · Datapath Synthesis · Intermediate

Partial Products and the Array Multiplier

Partial-product rows, column heights, and the array multiplier for unsigned products.

On this page

    Partial products

    Bit j of the multiplicand AND bit i of the multiplier is one partial product. Row i is the multiplicand masked by multiplier bit i, shifted left by i.

    An N by M unsigned multiplier forms N rows of M bits. The product needs N + M bits.

    A 4 by 4 example

    Four rows of four bits need 16 AND gates. Column c holds every product with i + j = c, and the heights below add to 16.

    Diagram
    4x4 unsigned: rows = 4, bits per row = 4, AND gates = 4 x 4 = 16
    column c holds partial products with i + j = c:
    c:       0  1  2  3  4  5  6
    height:  1  2  3  4  3  2  1
    total = 1 + 2 + 3 + 4 + 3 + 2 + 1 = 16
    product width = 4 + 4 = 8 bits

    What the array costs

    An array multiplier adds the rows pairwise with ripple adders. Its depth grows linearly with N, so it stays small and regular but slows past a few bits.

    Tall middle columns set the cost. Column 3 above holds 4 bits and needs the most compression.

    Common pitfall

    Reading column height as delay directly misleads. Height sets how many compression stages follow, and each stage plus the final adder sets the depth.

    Interview

    Likely probes: AND-gate count, column heights, and product width.

    • An N by M array needs N x M AND gates and an N + M bit product.

    • Column heights rise to min(N, M) in the middle, then fall symmetrically.

    • Array depth grows with N, which motivates trees for wide multipliers.

    Check yourself A 4 by 4 array uses how many AND gates, and how wide is the product?

    16 AND gates. The product is 8 bits wide.

    Check yourself Which column of the 4 by 4 array is tallest, and how tall is it?

    Column 3, with 4 partial products. It bounds the compression work.

    Related topics

    • Next: Booth radix-4 recoding

    • Adders and Carry Structures

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    See also

    • Compressor Trees
    • Signed Multiplication and Sign Extension
    • Truncation, the Final Adder, and Equivalence