Reset and Clock Discipline

Core concept

This lesson focuses on Reset and Clock Discipline as a first-class handshake behavior. The implementation goal is deterministic progress and explicit ownership boundaries between sequence, sequencer, and driver.

A robust implementation keeps one completion path, bounded waits, and clear status semantics so regressions remain debuggable under stress and reset churn.

[DRV][TLM][UVM] Reset and Clock Discipline flow

1) [TLM] driver pulls item from sequencer
2) [DRV] validates request and timing window
3) [DRV] executes protocol phase task
4) [DRV] classifies completion status
5) [TLM] item_done/response returns upstream
6) [UVM] sequence continues deterministic progress

• Preserve one-request/one-completion invariant.

• Keep failure semantics explicit in response status.

• Prefer boundary logs over noisy per-cycle traces.

Reference implementation

Use a minimal orchestration loop and delegate protocol detail to helper tasks. This keeps code review focused on contract semantics rather than incidental complexity.

class reset_clock_discipline_driver extends uvm_driver #(req_t);
  `uvm_component_utils(reset_clock_discipline_driver)

  task run_phase(uvm_phase phase);
    req_t req;
    rsp_t rsp;
    forever begin
      seq_item_port.get_next_item(req);
      rsp = rsp_t::type_id::create("rsp");
      rsp.set_id_info(req);
      drive_one(req, rsp);
      seq_item_port.item_done(rsp);
    end
  endtask
endclass

[DRV][TLM][UVM] timeline view

t0 req granted
 t1 setup phase
 t2 transfer wait
 t3 capture/response
 t4 completion edge
 t5 next arbitration cycle

• Initialize response identity from request before driving.

• Classify non-OK outcomes without skipping completion.

• Record wait cycles and retries when relevant.

Debug and validation pattern

Instrument progress counters and runbook-style checks to isolate handshake stalls quickly. Counter imbalance usually reveals the first broken boundary.

[DRV] validation checklist

- grant counter increments
- done counter increments
- timeout counter bounded
- response IDs correlate
- reset branches still complete

[UVM] triage order

1) issued vs granted
2) granted vs completed
3) completed vs response-consumed
4) inspect state snapshot and wait condition

Key takeaways

• Reset and Clock Discipline must preserve deterministic completion behavior.

• Counter-first observability reduces hang triage time.

• Bounded waits convert silent deadlocks into classified outcomes.

• Consistent response semantics simplify sequence policy code.

Common pitfalls

• Multiple hidden completion branches that drift over time.

• Unbounded waits on external readiness signals.

• Missing ID propagation between request and response objects.

• Late debug-only fixes without invariant checks.