Part 6 · Agents & Protocol IP · Intermediate

APB Agent Pattern: Simple Control-Bus Driver and Monitor Design

Reference APB-style agent architecture: setup/access phasing, deterministic request ordering, and straightforward monitor reconstruction.

APB pattern characteristics

APB-style protocols are control-oriented and timing-simple compared to pipelined data buses. Agent design can stay compact: one main driver loop, one monitor reconstruction path, and predictable ordering.

This simplicity makes APB an ideal baseline pattern for agent architecture fundamentals.

diagram

[VIP][APB] protocol shape

request fields:
  addr, write, wdata, strb/prot (optional)

phases:
  setup (psel + addr/control)
  access (penable asserted)
  completion (ready/resp sampled)

ordering:
  naturally serialized transaction stream

diagram

[AGT] APB component emphasis

driver:
  clear two-phase state machine

monitor:
  sample setup + access and merge into one item

sequencer:
  standard arbitration, usually no complex reordering logic

Use APB for clear, deterministic driver FSM teaching patterns.
Monitor reconstruction should preserve setup/access timing context.
Keep item schema compact and explicit.

APB item and driver template

A robust APB item captures address, direction, write data, read data, and response metadata. Driver should encode setup/access precisely with reset-safe behavior.

systemverilog

class apb_item extends uvm_sequence_item;
  `uvm_object_utils(apb_item)
  rand bit [31:0] addr;
  rand bit        write;
  rand bit [31:0] wdata;
  bit [31:0]      rdata;
  bit             slverr;

  function new(string name = "apb_item");
    super.new(name);
  endfunction
endclass

systemverilog

task drive_apb(apb_item tr);
  // setup phase
  @(posedge vif.pclk);
  vif.psel    <= 1'b1;
  vif.penable <= 1'b0;
  vif.paddr   <= tr.addr;
  vif.pwrite  <= tr.write;
  vif.pwdata  <= tr.wdata;

  // access phase
  @(posedge vif.pclk);
  vif.penable <= 1'b1;
  do @(posedge vif.pclk); while (!vif.pready);

  if (!tr.write) tr.rdata = vif.prdata;
  tr.slverr = vif.pslverr;

  // return to idle
  vif.psel    <= 1'b0;
  vif.penable <= 1'b0;
endtask

diagram

[DRV] APB timing sanity

setup cycle:
  psel=1, penable=0, control stable

access cycle(s):
  psel=1, penable=1, wait pready

completion:
  sample prdata/pslverr, deassert controls

Driver should isolate APB timing details from sequences.
Sample read data only at valid completion points.
Maintain explicit idle behavior to avoid waveform ambiguity.

APB monitor reconstruction pattern

Monitor should correlate setup and access phases into one coherent transaction object, then publish through analysis_port.

systemverilog

task run_phase(uvm_phase phase);
  apb_item tr;
  forever begin
    @(posedge vif.pclk);
    if (!vif.presetn) continue;

    if (vif.psel && !vif.penable) begin
      tr = apb_item::type_id::create("tr");
      tr.addr  = vif.paddr;
      tr.write = vif.pwrite;
      tr.wdata = vif.pwdata;

      // wait access completion
      do @(posedge vif.pclk); while (!(vif.psel && vif.penable && vif.pready));
      if (!tr.write) tr.rdata = vif.prdata;
      tr.slverr = vif.pslverr;
      ap.write(tr);
    end
  end
endtask

diagram

[MON] APB decode quality points

must capture:
  setup address/control
  access completion handshake
  response/error bits

should include:
  timestamp and interface id (if multi-instance)
  reset filtering policy

diagram

[VIP][APB] common monitor bugs

bug: sampling pwdata during access after source changes
fix: latch write payload in setup phase

bug: emitting transaction before pready
fix: publish only on completion condition

bug: ignoring reset transitions mid-transfer
fix: define explicit abort policy

Latch setup fields before waiting access completion.
Emit one analysis item per completed transfer.
Define reset-abort semantics and document them.

APB pattern debug and reuse notes

APB agents are often reused as control-plane VIP. Keep patterns crisp and well-documented so teams can adapt quickly without introducing protocol drift.

diagram

[DEBUG][APB] quick triage

symptom                               likely cause
-----------------------------------------------------------
no transfer completion                pready wait handling bug
wrong readback                        monitor sampling phase bug
sporadic slverr reports               response sampling misaligned
driver hangs after reset              reset-aware state machine issue

diagram

[VIP] APB reuse checklist

1) item fields map to protocol spec terms
2) driver setup/access timing documented
3) monitor reconstruction proven in tests
4) active/passive modes both supported
5) default cfg safe for new users

diagram

[AGT] APB evolution boundary

safe extensions:
  optional sideband fields
  additional coverage points
  stricter protocol checks

risky changes:
  altering transfer completion definition
  changing item semantic meanings

Key takeaways

APB pattern emphasizes clean two-phase timing and deterministic ordering.
Driver and monitor should encode complementary, spec-faithful behavior.
APB is ideal for reusable control-plane VIP foundations.
Strong monitoring and documentation preserve long-term reuse quality.

Common pitfalls

Publishing transactions before true APB completion handshake.
Sampling fields from unstable phases and corrupting decode.
Embedding project-specific quirks as default APB behavior.
Skipping passive-mode validation for APB monitor reuse.

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