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Course contents

  • Start Here4
  • UVM Foundations14
  • UVM Phases & Simulation Lifecycle26
  • Factory & Configuration15
  • Transaction-Level Modeling (TLM)13
  • UVM Sequences & Stimulus21
  • UVM Agents & Protocol VIP21
  • Environment & Test Classes11
    • Environment Architecture
      • The Environment and Its Config Object
      • Vertical Reuse: From Block to Subsystem
      • Integrating Third-Party VIP
      • Where the Virtual Sequencer Lives (and Whether You Need One)
    • Tests: Base Classes, Selection and Startup
  • Checking & Coverage in UVM21
  • UVM Register Abstraction Layer (RAL)22
  • Advanced UVM in Practice13
  • Debug & Regression10
  • Coding Practice47
  • Verification in Industry Practice10
  • Senior Prep: Architecture, Leadership and Interviews32
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‹Environment & Test Classes
  1. Topics
  2. UVM Verification
  3. Environment & Test Classes
  4. Environment Architecture

Part 7 · Environment & Tests · Intermediate

Environment Architecture

A learning map for the environment layer: dma_env and its config object, reusing the block env twice in a two-DMA subsystem, wrapping third-party VIP, and deciding where the virtual sequencer lives.

  • 4topics
  • 4lessons
On this page

    The block bench's dma_env is 30 lines: three agents, a scoreboard and three connections. The subsystem bench verifies two DMAs in a chain, and its environment contains that same dma_env twice, unedited, plus one end-to-end checker. Getting there took a handful of decisions that are easy to get wrong: what the env decides and what the test decides, how options reach the env, which agents go passive one level up, how a vendor's VIP fits in without leaking into every test, and who holds the sequencer handles. This topic makes those decisions on the bench.

    What you will be able to do

    • Design an environment and its config object: what the env builds and wires, what belongs in env config vs agent config vs the test, and why the env creates defaults only when its get fails.

    • Reuse a block env inside a subsystem env unchanged: passive agents on internal buses, the same virtual-interface names one level deeper, block scoreboards kept and an end-to-end checker added.

    • Integrate third-party VIP behind an adapter subscriber, a config map and a report catcher, and keep its version and compile under control.

    • Decide whether an env needs a virtual sequencer, where it lives at block, subsystem and SoC level, and what passive agents do to virtual sequences.

    The environment as it grows

    Tree: dma_subsys_test passes dma_subsys_cfg to dma_subsys_env, which builds dma0 and dma1 (both dma_env, dma1's input passive) and an end-to-end scoreboard fed by both.
    The subsystem environment: the test hands it a config object; it builds two copies of the block env, makes dma1's input agent passive, and adds a checker for the whole chain. Each block scoreboard keeps checking its own DMA.

    The lessons, in order

    Lesson

    What it answers

    The Environment and Its Config Object

    What dma_env builds and wires, dma_subsys_cfg as a worked env config, and config_db vs handle passing.

    Vertical Reuse: From Block to Subsystem

    The two-DMA bench: one env reused twice, the subsystem top, 10/10/10 matches, and what changes again at SoC level.

    Integrating Third-Party VIP

    Adapter subscriber, config mapping, report catchers, version pinning, and what to ask the vendor.

    Where the Virtual Sequencer Lives

    Env-owned virtual sequencer vs handles, hierarchical virtual sequencers, and passive agents.

    Read this topic before Tests: Base Classes, Selection and Startup: tests make more sense once you know what the environment promises them. Start with: The Environment and Its Config Object.

    PreviousNext: The Environment and Its Config Object

    Up next

    Up nextThe Environment and Its Config Object

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    See also

    • Tests: Base Classes, Selection and Startup