Part 3 · Factory & Configuration · Intermediate

Registration Macros: Wiring Classes Into the Factory

uvm_component_utils vs uvm_object_utils, begin/end field variants, and the type_id helpers each macro generates.

Macro selection guide

Pick the macro that matches base class category — component for hierarchy nodes, object for transient data and sequences.

diagram

[FACTORY][UVM] macro map

uvm_component hierarchy node:
  `uvm_component_utils(T)
  or `uvm_component_utils_begin/end(T) + fields

uvm_object transient type:
  `uvm_object_utils(T)
  or `uvm_object_utils_begin/end(T) + fields

wrong macro -> broken phases or missing factory hooks

systemverilog

class base_driver extends uvm_driver #(apb_txn);
  `uvm_component_utils(base_driver)
  function new(string name, uvm_component parent);
    super.new(name, parent);
  endfunction
endclass

class apb_txn extends uvm_sequence_item;
  rand bit [31:0] addr;
  `uvm_object_utils_begin(apb_txn)
    `uvm_field_int(addr, UVM_ALL_ON)
  `uvm_object_utils_end
  function new(string name = "apb_txn"); super.new(name); endfunction
endclass

Key takeaways

Component utils for env/agent/driver/monitor/test classes.
Object utils for items, sequences, config objects, transactions.
Begin/end variants add field automation without losing registration.

Common pitfalls

Using object_utils on uvm_component — phase callbacks break.
Forgetting utils macro — type_id::create won't compile.
Duplicating registration macros in derived classes incorrectly.

What macros generate

Each utils macro defines a nested type_id class with static helpers used by factory override APIs.

Generated type_id surface

systemverilog

// Conceptual surface created by macro
class base_driver extends uvm_driver #(apb_txn);
  typedef uvm_component_registry#(base_driver, "base_driver") type_id;

  static function base_driver create(string name, uvm_component parent);
    return type_id::create(name, parent);
  endfunction

  static function uvm_object_wrapper get_type();
    return type_id::get();
  endfunction
endclass

create() — factory build entry for the type.
get_type() — proxy handle for override registration APIs.
set_type_override() / set_inst_override() — convenience wrappers.

Field automation pairing

systemverilog

class env_cfg extends uvm_object;
  rand bit enable_scoreboard;
  rand int unsigned timeout_ns;
  `uvm_object_utils_begin(env_cfg)
    `uvm_field_int(enable_scoreboard, UVM_ALL_ON)
    `uvm_field_int(timeout_ns, UVM_ALL_ON)
  `uvm_object_utils_end
  function new(string name = "env_cfg"); super.new(name); endfunction
endclass

diagram

[UVM][FACTORY] cfg object pattern

cfg is uvm_object -> object_utils
cfg created via env_cfg::type_id::create("cfg")
cfg pushed through config_db (separate mechanism)

Common pitfalls

Heavy field macros on hot-path transaction classes without need.
Mixing utils_begin/end with plain utils in same class.
Copy/pasting macro type parameter from a different class name.

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