Part 3 · Factory & Configuration · Intermediate

type_id::create Pattern: Canonical Factory Build Path

Standard create() idioms for components and objects, parent/name contracts, and verbose factory API equivalents.

Component create pattern

Build hierarchy nodes with T::type_id::create(name, parent). The factory resolves type, constructs the object, and links parent/child relationships.

diagram
[FACTORY][UVM] component create contract

inputs:
  requested type T (registered)
  instance name (local, not full path)
  parent uvm_component

factory duties:
  apply overrides for (T, eventual full path)
  call new(name, parent) on resolved type
  register child under parent
systemverilog
class my_agent extends uvm_agent;
  `uvm_component_utils(my_agent)
  base_driver drv;
  base_monitor mon;

  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    drv = base_driver::type_id::create("drv", this);
    mon = base_monitor::type_id::create("mon", this);
  endfunction
endclass

Key takeaways

  • Always pass parent for components — hierarchy and paths depend on it.

  • Use stable local names — they become override path segments.

  • Request base types in env; let tests override to derivatives.

Common pitfalls

  • Null parent on components — illegal for uvm_component construction.

  • Dynamic instance names — breaks instance override paths.

  • Creating same child twice with conflicting names.


Object create pattern and verbose APIs

Transient objects use T::type_id::create(name) without parent. Sequences and items follow the same factory path.

Object and sequence examples

systemverilog
apb_txn t = apb_txn::type_id::create("t");
env_cfg cfg = env_cfg::type_id::create("cfg");
apb_base_seq seq = apb_base_seq::type_id::create("seq");
systemverilog
// Verbose equivalent (components) — rarely needed in user code
uvm_factory f = uvm_factory::get();
uvm_object obj;
void'(f.create_component_by_type(
  base_driver::get_type(),
  get_full_name(),
  "drv",
  this,
  obj
));
drv = base_driver(obj);

Naming conventions for override-friendly paths

  • Keep agent child names constant: drv, mon, sqr, cov.

  • Avoid generate-loop names unless instance overrides use patterns.

  • Document full path examples in test comments.

diagram
[FACTORY] predictable path example

uvm_test_top.env.agt_tx.drv
uvm_test_top.env.agt_rx.drv

instance override target uses suffix from parent full name

Common pitfalls

  • Using create() for non-registerable plain SystemVerilog classes.

  • Hardcoding derivative types in env instead of base requests.

  • Verbose factory API calls that obscure requested base type.