Part 11 · Senior Prep · Intermediate

Stimulus Silent Failures: Zero Traffic and Instant Pass

Stimulus-bucket playbook when tests pass too fast with no activity — run_phase never started, null vif, reset gated, or sequences never launched.

Stimulus bucket first moves

Silent failures — sim ends quickly with zero transactions — are often worse than hangs because CI marks them pass. Triage run_phase, reset, vif, and sequence start in that order.

diagram
[DEBUG][SENIOR][UVM] silent failure triage

instant pass + zero txns:
  1) did run_phase raise objection and start vseq?
  2) is vif non-null and reset deasserted?
  3) is agent UVM_ACTIVE (not passive by mistake)?
  4) did sequence body() execute (log at start)?
  5) check_phase: assert txn_count > 0
systemverilog
function void check_phase(uvm_phase phase);
  super.check_phase(phase);
  if (env.agt.mon.txn_count == 0)
    `uvm_error("STIM_CHECK", "zero transactions — silent stimulus failure")
endfunction

virtual task run_phase(uvm_phase phase);
  `uvm_info("TEST", "run_phase entered", UVM_LOW)
  phase.raise_objection(this);
  smoke_vseq seq = smoke_vseq::type_id::create("seq");
  seq.start(env.v_sqr);
  phase.drop_objection(this);
endtask

Key takeaways

  • Silent pass is a CI hazard — add check_phase transaction guards.

  • Log run_phase entry and sequence body() start unconditionally.

  • Null vif and reset-gated stimulus are the top two root causes.

Common pitfalls

  • No check_phase guard — zero-txn tests pass nightly forever.

  • Passive agent config copied from chip-level into block test.

  • Virtual sequence started on wrong sequencer handle.


Stimulus path verification

Walk the full stimulus chain from test to pin toggles. Breaks can occur at any link.

Stimulus chain diagram

diagram
[DEBUG][SENIOR][UVM] stimulus chain

test.run_phase
  -> vseq.start(v_sqr)
      -> subseq.start(agt.sqr)
          -> driver.get_next_item
              -> drive on vif
                  -> monitor sees txn

break anywhere -> zero traffic
systemverilog
task body();
  `uvm_info("SEQ", $sformatf("%s body start", get_type_name()), UVM_LOW)
  repeat (10) begin
    req = my_item::type_id::create("req");
    start_item(req);
    assert(req.randomize());
    finish_item(req);
  end
  `uvm_info("SEQ", $sformatf("%s body done", get_type_name()), UVM_LOW)
endtask

Reset and clock gating checks

  • Confirm reset deasserted before run_phase objection raised.

  • Check clock is running on the interface seen by the driver.

  • Verify enable bits in cfg are not clearing is_active.

  • Ensure +UVM_TESTNAME selects a test that actually runs sequences.

bash
# stimulus smoke grep bundle
grep -E "run_phase entered|body start|get_next_item|txn_count" sim.log
diagram
[DEBUG] silent failure pass criteria

check_phase fires on zero txn tests in CI
and
every sequence logs body start at UVM_LOW
and
smoke list asserts min txn threshold

Common pitfalls

  • Factory override replaced driver with a stub that never drives.

  • Reset held by power-aware cfg meant for a different test.

  • Starting virtual sequence before env reset_phase completes.