Part 5 · Sequences · Intermediate

FIFO Default Arbitration: Interleaving at Item Boundaries

UVM_SEQ_ARB_FIFO behavior, start_item/finish_item slot model, and interleaving timeline diagrams.

Default mode: first pending wins

By default, uvm_sequencer uses UVM_SEQ_ARB_FIFO — first-come-first-served among sequences that have completed start_item and are waiting for the driver. Within a single sequence, items are strictly ordered: item N+1 cannot start until item N's finish_item completes.

Each start_item / finish_item pair consumes exactly one arbitration slot. The driver executes one item, calls item_done, and the sequencer grants the next pending start_item.

diagram
[UVM] FIFO arbitration — pending queue

  Sequences with completed start_item (waiting for driver):

    Queue front ──► [bg_seq item 3] [test_seq item 1] [bg_seq item 4] [test_seq item 2]
                         │
                         ▼
                    DRIVER takes front
                         │
                         ▼
                    item_done  dequeue  next winner

Interleaving diagram — two sequences on one sequencer

Two sequences started with fork/join on the same sequencer interleave at item boundaries, not at sequence boundaries:

systemverilog
fork
  bg_seq.start(sqr);    // body: repeat(100) start_item/finish_item
  test_seq.start(sqr);  // body: 3 directed reads
join

// Actual driver order WITHOUT lock/grab:
// bg[0] → test[0] → bg[1] → test[1] → bg[2] → test[2] → bg[3] → ...
diagram
[STIM] FIFO interleaving timeline

  TIME ───────────────────────────────────────────────────────────────►

  bg_seq:     start──[item0]──start──[item1]──start──[item2]──start──[item3]──...
                  │            ▲           │            ▲
  test_seq:       └──start──[t0]──start──[t1]──start──[t2]──done
                       │         │         │
  DRIVER:          bg0   test0   bg1   test1   bg2   test2   bg3  ...

  Legend: [STIM] = pin activity   [SEQ] start = blocked until prior item_done

  Key insight: bg_seq body() keeps running — it blocks at start_item, not at fork

Rules of FIFO arbitration

  • First sequence to complete start_item when driver is idle wins immediately.

  • If driver is busy, start_item completes (request queued) — sequence blocks at finish_item's implicit wait.

  • Actually: start_item blocks until grant; finish_item blocks until item_done.

  • Fork order does NOT determine item order — timing of start_item calls does.


Within-sequence ordering is guaranteed

FIFO arbitration guarantees that items from the same sequence never reorder. Sequence A's item 5 always executes after item 4 completes. Interleaving only happens between sequences.

diagram
[SEQ] intra-sequence order preserved

  burst_seq body():
    for (i = 0; i < 8; i++)
      start_item(req[i]); finish_item(req[i]);

  DRIVER always sees: req[0]  req[1]  req[2]  ...  req[7]
  (no other sequence can insert between burst beats
   UNLESS burst_seq releases driver between items — i.e. normal start_item boundaries)

If you need multiple beats without any interleaving from other sequences, FIFO alone is insufficient — use lock/grab (next lesson).


Observing FIFO behavior in simulation

Add sequence-ID logging at start_item entry to see interleaving in the log. Raise sequencer verbosity to UVM_FULL for arbitration debug messages from the library.

systemverilog
task body();
  `uvm_info("SEQ", $sformatf("%s requesting item", get_full_name()), UVM_MEDIUM)
  start_item(req);
  assert(req.randomize());
  `uvm_info("SEQ", $sformatf("%s driving addr=0x%0h", get_full_name(), req.addr), UVM_MEDIUM)
  finish_item(req);
endtask
diagram
[UVM] log excerpt — FIFO interleaving visible

  UVM_INFO @ 100ns  apb_bg_seq [SEQ] apb_bg_seq requesting item
  UVM_INFO @ 100ns  apb_test_seq [SEQ] apb_test_seq requesting item
  UVM_INFO @ 105ns  apb_bg_seq [SEQ] apb_bg_seq driving addr=0x1000
  UVM_INFO @ 110ns  apb_test_seq [SEQ] apb_test_seq driving addr=0x2000
  UVM_INFO @ 115ns  apb_bg_seq [SEQ] apb_bg_seq driving addr=0x1004
  ...
  Pattern: alternating sequence names = FIFO interleaving at item boundaries

Key takeaways

  • UVM_SEQ_ARB_FIFO: first pending start_item wins — default everywhere.

  • Multiple forked sequences interleave items, not whole sequence bodies.

  • Same-sequence item order is preserved; cross-sequence order is not.

Common pitfalls

  • Expecting test_seq to complete all 3 items before bg_seq continues — FIFO interleaves.

  • Using repeat(1) start_item loops expecting atomic multi-beat — each iteration is one slot.

  • Changing fork order to fix interleaving — timing of start_item matters, not fork order.