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Course contents

  • Start Here4
  • UVM Foundations18
  • UVM Phases & Simulation Lifecycle94
  • Factory & Configuration37
  • Transaction-Level Modeling (TLM)42
    • TLM 1: Ports, Exports and Analysis
    • put/get/transport Hub: Flow-Controlled Point-to-Point TLM
    • TLM 2.0 Sockets
    • Analysis Ports & Subscribers: Broadcast Observability in UVM
    • TLM FIFOs & Analysis FIFO Usage Hub
      • uvm_tlm_fifo Basics: Blocking put/get and Queue Semantics
      • uvm_tlm_analysis_fifo Pattern: Monitor Broadcast to Pull-Based Checker
      • Producer-Consumer FIFO: Thread Decoupling and Throughput Stability
      • FIFO vs Direct Connect: Choosing the Right Boundary
      • FIFO Depth & Backpressure: Sizing, Overflow, and Latency Trade-offs
      • FIFO Debug Patterns: Stuck Consumer, Empty Queue Hangs, and Runaway Growth
    • TLM Debugging Hub: Unconnected Ports, Type Mismatch, and Silent Drops
  • UVM Sequences & Stimulus44
  • UVM Agents & Protocol VIP71
  • Environment & Test Classes55
  • Checking & Coverage in UVM37
  • UVM Register Abstraction Layer (RAL)53
  • Advanced UVM in Practice44
  • Debug & Regression10
  • Coding Practice47
  • Senior Prep: Architecture, Leadership and Interviews92
  • Verification in Industry Practice10
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