Part 4 · TLM & Analysis · Intermediate

TLM Connection Audit: connect_phase Checklist and Structural Proof

A practical connect_phase auditing framework: expected topology matrix, endpoint checks, and fail-fast structural validation.

Audit mindset

Treat TLM wiring as a contract that can be machine-checked. The audit should answer: which endpoints must connect, in what direction, with what minimum cardinality.

A connection audit belongs in environment code and runs automatically in every test to prevent latent topology regressions.

diagram

[UVM][TLM] connection contract template

endpoint                           requirement
---------------------------------------------------------
drv.seq_item_port                  exactly 1 target
mon.ap                             >= 1 subscriber
agent.req_ap                       scoreboard + coverage
predictor.bus_in                   connected to monitor.ap

status:
  pass only when all mandatory rules hold

diagram

[TLM] audit timeline

build_phase:
  create components/endpoints

connect_phase:
  establish all connections

end_of_elaboration/start_of_sim:
  run audit + print topology

run_phase:
  assume structure is valid, focus on behavior

Connection audits prevent structural regressions from reaching runtime debug.
Express requirements as explicit rules, not tribal knowledge.
Run audit consistently in every test configuration.

connect_phase checklist implementation

Keep connect_phase readable: perform connections in a stable order, then run one audit function that validates all mandatory links.

systemverilog

function void connect_phase(uvm_phase phase);
  super.connect_phase(phase);

  // Sequencer-driver path
  agt.drv.seq_item_port.connect(agt.sqr.seq_item_export);

  // Analysis fanout
  agt.mon.ap.connect(sb.analysis_export);
  agt.mon.ap.connect(cov.analysis_export);
  agt.mon.ap.connect(pred.bus_in);

  // Run local audit right away
  audit_connections("connect_phase");
endfunction

systemverilog

function void audit_connections(string stage);
  if (agt.drv.seq_item_port.size() != 1)
    `uvm_fatal("TLM_AUDIT",
      $sformatf("[%s] seq_item_port expected 1 got %0d",
        stage, agt.drv.seq_item_port.size()))

  if (agt.mon.ap.size() < 2)
    `uvm_fatal("TLM_AUDIT",
      $sformatf("[%s] monitor.ap expected >=2 got %0d",
        stage, agt.mon.ap.size()))

  agt.mon.ap.print_connections();
endfunction

diagram

[UVM] checklist categories

category A: mandatory links
  - no link -> fatal

category B: optional observers
  - no link -> warning

category C: debug-only taps
  - no link -> info

Separate mandatory and optional links to avoid noisy false failures.
Annotate audits with stage names for easier log interpretation.
Print connection maps for manual confirmation alongside automated checks.

Topology matrix and drift control

Represent expected topology as a small matrix so changes are reviewable and auditable. This makes refactor impact visible in code review.

diagram

[UVM][TLM] expected topology matrix

producer endpoint      sink endpoint            class     mandatory
-------------------------------------------------------------------
mon.ap                 sb.analysis_export       analysis  yes
mon.ap                 cov.analysis_export      analysis  no
mon.ap                 pred.bus_in              analysis  yes
drv.seq_item_port      sqr.seq_item_export      seq_item  yes
ref_model.req_ap       checker.req_export       analysis  yes

systemverilog

typedef struct {
  string producer;
  string sink;
  bit mandatory;
} tlm_link_rule_t;

tlm_link_rule_t link_rules[$] = '{
  '{"mon.ap", "sb.analysis_export", 1},
  '{"mon.ap", "cov.analysis_export", 0},
  '{"mon.ap", "pred.bus_in", 1}
};

diagram

[UVM] drift detection strategy

when topology changes:
  1) update connect code
  2) update link_rules matrix
  3) update expected fanout counts
  4) rerun audit test

if one step is skipped, audit fails by design

Matrix-based expectations make topology intent explicit.
Keep audit rules versioned with env wiring code.
Review topology diffs like API contract changes.

Audit outputs and failure triage

Audit messages should be deterministic and grep-friendly. Consistent report IDs allow CI to classify and block structural failures quickly.

diagram

[UVM][TLM] recommended report IDs

TLM_AUDIT_PASS
TLM_AUDIT_WARN
TLM_AUDIT_FAIL
TLM_CONN_MAP

example:
  UVM_INFO  @0: env [TLM_CONN_MAP] mon.ap -> sb.analysis_export
  UVM_FATAL @0: env [TLM_AUDIT_FAIL] seq_item_port expected 1 got 0

systemverilog

function void emit_audit_pass();
  `uvm_info("TLM_AUDIT_PASS",
    "All mandatory TLM links are valid", UVM_LOW)
endfunction

diagram

[UVM] CI triage policy

if TLM_AUDIT_FAIL present:
  fail test immediately

if TLM_AUDIT_WARN count exceeds threshold:
  mark unstable / investigate

store connection map artifacts for comparison across runs

TLM Connection Audit: connect_phase Checklist and Structural Proof

Audit mindset

connect_phase checklist implementation

Topology matrix and drift control

Audit outputs and failure triage

Key takeaways

Common pitfalls