Answer each question out loud before opening it. If you miss more than three in the checkpoint, revisit the lessons linked at the end.
Only that everything the model measures happened at least once; not that it was checked, nor that the model lists what matters.
It measures execution of existing code: not values, combinations or missing code.
From rules and risks: occupancy bins with boundaries apart, push and pop events at empty, middle and full, wrap-around, reset while non-empty, crossed only where logic interacts.
Only crosses where the combination exercises logic its parts do not; group values, mark impossible ones illegal, condition on events, pairwise for configurations.
Classify the holes (rare, very rare, never generated, unreachable, wrong) and act on each; more seeds barely move a plateau.
Prove it unreachable, preferably with formal, then exclude or mark illegal with the reason; never exclude what is merely rare.
Feed holes back into constraints for part of each test, keep a blind share, and send stubborn holes to directed tests or formal.
By the bugs it detects: mutation testing or seeded bugs; each survivor names a missing test or check.
Task. An interrupt controller has 32 sources, each with an enable bit and a priority (0 to 3), a mask register, a pending register (write 1 to clear) and one interrupt output. Write the coverage model: coverpoints, bins, crosses, and the events you would cover. Then say which crosses you would not write.
Coverpoints: source raised (32 bins); priority of the highest pending source (4); enable and mask state when a source is raised (enabled and unmasked, disabled, masked); pending clear written (per source, and for a source not pending). Events: two sources raised in the same cycle at different priorities and at equal priority; a source raised while its pending bit is being cleared; a higher-priority source arriving while the output is already asserted for a lower one; mask written while an interrupt is pending; reset with sources pending. Crosses: source × enable/mask state (32 × 3 = 96), priority-of-winner × priority-of-loser for simultaneous raises (4 × 4, only the cross that tests arbitration). Not written: source × priority × enable × mask × every other source (explodes to millions of bins and exercises no shared logic); data patterns of registers beyond walking ones and all-ones for stuck bits.
BUG_23 ("CTRL port k disabled") and BUG_16 ("PKT_CNT3 cleared").
Toggle coverage on port_en.
They are boundaries where bugs concentrate; 2 to 14 behave alike.
13,824.
91.8% and 92.4%.
Hit, excluded as unreachable with proof, or waived with a reason and an owner.
54.9 and 12.4.
70%; each was a missing boundary or simultaneous-event test.
30 before, 12 after.
All 24.